[SOLVED] Clock domain crossing, clock tracking method (VHDL)?

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legendbb

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Don't know the best way to describe this, thanks for your attention.

2 synchronous clocks:
a. 1x clock rate
b. 2x clock rate

In 2x-clk domain, want to implemented logic to act aligning to 1x clk rising_edge or falling_edge.

My first instinct is to use if statement inside process, for example:
Code: 
proc_exp: process(Clk_2x)
begin
	[B]if ('1' = Clk_1x) then[/B] -- clock to lut directly, Clk_1x has guaranteed phase offset to avoid metastability for Clk_2x
	-- or
	[B]if ('1' = reg_toggle_Clk_1x) then [/B] -- reg_toggle_Clk_1x, a register toggles at both edges of 1x_clk
		do_sth;
	end if;
end process proc_exp;

Not sure if the difference between these two ways of implementation matters. And wondering the best way of doing this.

Thanks for any comments.

Regards,:thumbsup:
 
Last edited:

Try to only use clocks as clocks. This means that your second alternative is better, but the code should look like this:

Code: 
process(Clk_2x)
begin
  if rising_edge(Clk_2x) then
    if ('1' = reg_toggle_Clk_1x) then -- change to '0' if the other edge is wanted
      -- do something
    end if;
  end if;
end process;

You can use the "flancter" circuit to create a signal that toggles for every edge of Clk_1x.

It is also possible to create a signal that toggles only for one edge of Clk_1x and then detect both edges of this signal in the Clk_2x domain.
 

I always wondered why use this weird looking circuit instead of something like this:

Code: 
process (short_pulse_acknowledge , our_short_pulse) is
begin
if short_pulse_acknowledge = '1' then
  short_pulse_detected <= '0' ;
elsif rising edge ( our_short_pulse ) then
   short_pulse_detected <= '1' ;
end if ;
end process ;

-- short_pulse_acknowledge (essentially an asynchronous reset) will be generated by the receiving clock domain once it samples"short_pulse_detected".
 

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