legendbb
Member level 1
Don't know the best way to describe this, thanks for your attention.
2 synchronous clocks:
a. 1x clock rate
b. 2x clock rate
In 2x-clk domain, want to implemented logic to act aligning to 1x clk rising_edge or falling_edge.
My first instinct is to use if statement inside process, for example:
Not sure if the difference between these two ways of implementation matters. And wondering the best way of doing this.
Thanks for any comments.
Regards,:thumbsup:
2 synchronous clocks:
a. 1x clock rate
b. 2x clock rate
In 2x-clk domain, want to implemented logic to act aligning to 1x clk rising_edge or falling_edge.
My first instinct is to use if statement inside process, for example:
Code:
proc_exp: process(Clk_2x)
begin
[B]if ('1' = Clk_1x) then[/B] -- clock to lut directly, Clk_1x has guaranteed phase offset to avoid metastability for Clk_2x
-- or
[B]if ('1' = reg_toggle_Clk_1x) then [/B] -- reg_toggle_Clk_1x, a register toggles at both edges of 1x_clk
do_sth;
end if;
end process proc_exp;
Not sure if the difference between these two ways of implementation matters. And wondering the best way of doing this.
Thanks for any comments.
Regards,:thumbsup:
Last edited: