That is good in theory, but for a practical design it is more useful to generate a clock enable (a signal that is high for only one clock cycle) or use a PLL.
It is not recommended to use a logic/register/flip-flop output as a clock.
A clock enable is used like this in VHDL:
Code:
process(clk, rst_n)
if rst_n = '0' then
-- set all registers to the reset value
elsif rising_edge(clk) then
-- it can be useful to have some stuff here
-- e.g. setting generated clock enables to zero
if clock_enable = '1' then
-- do the work here
end if;
end if;
end process;
When clock_enable = '0' the process will keep it's state.
The clock enable is normally produced by the same clock as the circuit that uses it.
With clock enables you can have a robust system with many different "clocks" (clock enables). It is robust because everything is clocked by the same clock.