clock division with vhdl??

[martur]

hello

i have a problem with vhdl. in fact, i wrot the testbench file to simulate my design. in this file i need to assign a particular value to a signal during a particular periode. so i used the following expression:

clk <= '0'; wen <= '1'; wait for 25 NS; wen<= '0'; wait for 25 NS;
clk <= '1'; wait for 50 NS;
(the clock periode is equal to 100ns)

so the simulation gives me the correct results.but as you know, i can't synthesis my design and implemente it in FPGA with "wait" instruction...so my question is, what should i do to make the signal "wen" maintained to 0 during 1/4 of periode and after that, maintained to 1 during 1/4 of period. how can i devide the clock???

thank you in advance

 

[FvM]

If the design is dedicated to a recent FPGA family, you would use a PLL clock multiplier. Otherwise, there's no good way. Logic cell delays can be used, but are strongly affected by process, voltage and temperature ("PVT") variations. Or supply a factor 4 higher clock frequency.

 

[preet]

Dear Marter,

You have to implement counter of n bits i f you need to divide any clock by 2 to the power 'n'.
if you have specfic frequency requirement the tell me the detail of input freq, output frequency and 'on' time

Regards

Preet

 

[alexan_e]

if you have specfic frequency requirement the tell me the detail of input freq, output frequency and 'on' time

The OP was clear on the requirements, he has a clock with a period of 100ns (10MHz) and he wants to use delays of 25ns which is the period of 40MHz so as FvM said he can either use an internal frequency clock multiplier if available or an external clock of 40 MHz.
martur, we assume that the 100ns clk is currently the main (highest) clock frequency available in your system and not a clock which is already divided.

Alex

 

[TrickyDicky]

Dear Marter,

You have to implement counter of n bits i f you need to divide any clock by 2 to the power 'n'.
if you have specfic frequency requirement the tell me the detail of input freq, output frequency and 'on' time

Regards

Preet

This is only good if you use the output of this counter as a clock enable in your base clock domain. It is generally bad practice to use the output from a counter to clock other registers. It is much safer to use a PLL

 

[preet]

Dear TrickyDicky,

plz elaborate your point with example. this will allow me to understand better.

Regards,

Preet

 

[TrickyDicky]

I dont have an example - its just bad news to use a counter as a clock for other devices. It may work at times, but can become unreliable without warning and is affected by temperature. So instead of using it as
a clock, use as a clock enable:

cnt_proc : process(clk)
begin
  if rising_edge(clk) then
    cnt <= cnt + 1;
  end if;
end process;

div_2_proc : process(clk)
begin
  if rising_edge(clk) then
    if cnt(0) = '1' then
      a <= not a;
    end if;
  end if;
end process;

Here, a will toggle at half the rate of cnt(0)

 

[preet]

Dear TrickyDicky,

how much i can divide by using PLL

Regards

Preet

 

[TrickyDicky]

as much as the PPL will allow. See documentation for your particular FPGA. Usually you can get anything from a few MHz to 100s of MHz.

 

[std_match]

check my clock divider code: **broken link removed**

That is good in theory, but for a practical design it is more useful to generate a clock enable (a signal that is high for only one clock cycle) or use a PLL.

It is not recommended to use a logic/register/flip-flop output as a clock.

A clock enable is used like this in VHDL:

process(clk, rst_n)
  if rst_n = '0' then
    -- set all registers to the reset value
  elsif rising_edge(clk) then
    -- it can be useful to have some stuff here
    -- e.g. setting generated clock enables to zero
    if clock_enable = '1'  then
      -- do the work here
    end if;
  end if;
end process;

When clock_enable = '0' the process will keep it's state.

The clock enable is normally produced by the same clock as the circuit that uses it.

With clock enables you can have a robust system with many different "clocks" (clock enables). It is robust because everything is clocked by the same clock.

 

[jimmy_tag]

That is good in theory, but for a practical design it is more useful to generate a clock enable (a signal that is high for only one clock cycle) or use a PLL.

It is not recommended to use a logic/register/flip-flop output as a clock.

A clock enable is used like this in VHDL:

process(clk, rst_n)
  if rst_n = '0' then
    -- set all registers to the reset value
  elsif rising_edge(clk) then
    -- it can be useful to have some stuff here
    -- e.g. setting generated clock enables to zero
    if clock_enable = '1'  then
      -- do the work here
    end if;
  end if;
end process;

When clock_enable = '0' the process will keep it's state.

The clock enable is normally produced by the same clock as the circuit that uses it.

With clock enables you can have a robust system with many different "clocks" (clock enables). It is robust because everything is clocked by the same clock.

The code on my site is Synthesizable. And it gives 100% output. You should try it first.

And about clock enable, u can directly add signal to my code..

 

[TrickyDicky]

The code on my site is Synthesizable. And it gives 100% output. You should try it first.

And about clock enable, u can directly add signal to my code..

Just because it is synthesisable doesnt mean its a good idea to teach people that generating clocks in logic is a good idea. You should modify it to say that "op" should be used as an enable to any other internal logic rather than as a clock.

 

[FvM]

You should modify it to say that "op" should be used as an enable to any other internal logic rather than as a clock

But it isn't designed as a one-cycle-high clock enable rather than a 50% duty cycle ripple divided clock.

Generally, I can imagine some cases where the said clock divider serves it's purpose, e.g. generating an external clock output for a peripheral device, but more cases where a clock enable would be preferred.

Presuming, that you don't have a PLL to generate a clock with zero delay, it may be necessary to use the bad divided clock solution for a slow clock domain. But timing closure of domain crossing signals will add some extra design effort.

The thread title is somewhat misleading by the way, because the original post is actually requesting clock multiplication rather than division.