clock division in timer
You can find an explaination of a simpler clock doubler at:
**broken link removed**
Scroll down and look at circuit #4. Within FPGAs, clock frequency doubling is most often handled by DLL or PLL circuits. However, your 1Hz requirement means a DLL or PLL will not work as they have a 25MHz frequency minimum.
This doubler and most others use XOR gates. The pulse width of the output signal is based on the prop delay of the gates around the loop. You can add extra delay within this loop to widen the pulses some what. However, with a 10Hz rate, your pulses will resemble the impulse function when viewed on a scope. They will be sufficient to trigger all internal logic, just do not expect to see a large duty cycle on the doubled clock.