# Clock division by an non integer number using VHDL

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#### GuoHui

##### Newbie level 4 clock division

I want to generate a 1Hz channel from 5Hz, which is divide by 2.5, and i want to have 50% duty cycle, can anyone help me?

guohui

#### banjo vhdl clock doubler

Typically this is accomplished by first multiplying by 2 to get 10 Hz. Then use a counter to divide by 5 to get 2Hz. Finally, use a divide by 2 flop to get 1Hz at 50% duty cycle.

The multiply by two is formed from a XOR and quadrature clock.

#### GuoHui

##### Newbie level 4 divide clock by 5 vhdl

banjo said:
Typically this is accomplished by first multiplying by 2 to get 10 Hz. Then use a counter to divide by 5 to get 2Hz. Finally, use a divide by 2 flop to get 1Hz at 50% duty cycle.

The multiply by two is formed from a XOR and quadrature clock.

Hi, thanks for your reply. Can you please show me the circuit or VHDL code for multiply 2?

guohui

#### GuoHui

##### Newbie level 4 divide by 2.5

banjo said:
Typically this is accomplished by first multiplying by 2 to get 10 Hz. Then use a counter to divide by 5 to get 2Hz. Finally, use a divide by 2 flop to get 1Hz at 50% duty cycle.

The multiply by two is formed from a XOR and quadrature clock.

is it the circuit looks like this?

#### banjo clock division in timer

You can find an explaination of a simpler clock doubler at:

https://www.xilinx.com/xlnx/xweb/xi...guageID=1&multPartNum=1&sTechX_ID=pa_six_easy

Scroll down and look at circuit #4. Within FPGAs, clock frequency doubling is most often handled by DLL or PLL circuits. However, your 1Hz requirement means a DLL or PLL will not work as they have a 25MHz frequency minimum.

This doubler and most others use XOR gates. The pulse width of the output signal is based on the prop delay of the gates around the loop. You can add extra delay within this loop to widen the pulses some what. However, with a 10Hz rate, your pulses will resemble the impulse function when viewed on a scope. They will be sufficient to trigger all internal logic, just do not expect to see a large duty cycle on the doubled clock.

#### kib counter division vhdl

Why do you require a divide by 2.5 circuit.
Why not directly use a divide by 5 cicuit to get 1Hz from 5Hz.
check this

regards
kib

#### banjo clock division in vhdl

The original post mentioned that a 50% duty cycle on the 1Hz signal is required. The easiest way to do that is to divide down to twice the frequency you want and then follow that with a divide by 2 flip-flop. The divide by 2 flip-flop always has a 50% duty cycle regardless of the duty cycle of the incoming signal. This is what drove the initial requirement of divide by 2.5.

#### spveer

##### Newbie level 1 divide by 2 vhdl code

how about simply using tboth falling and rising edges of the source clock, and dividing by 5 directly to get the 50% duty cycle... I think thats the simplest solution.!?

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