Davood Amerion said:First you have to double input frequency, and then divide it by 3.
then divide it by 2 to produce 50% duty.
for doubling input frequency simply put one delay (such as RC, or buffer gates)
for example 20nS, then XOR input frequency and delayed one, you get 2x multiplayer.
Regards
Davood Amerion
module clk_div3(clk,clk_out);
input clk;
output clk_out;
reg [1:0] cnt_p, cnt_n;
wire [1:0] cnt_p_nx, cnt_n_nx;
initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end
assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};
always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;
endmodule // clk_div3
nand_gates said:Here is one more ckt in verilog!!
Code:module clk_div3(clk,clk_out); input clk; output clk_out; reg [1:0] cnt_p, cnt_n; wire [1:0] cnt_p_nx, cnt_n_nx; initial begin cnt_p = 2'b11; cnt_n = 2'b11; end assign clk_out = cnt_p[0] | cnt_n[0]; assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])}; assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])}; always @(posedge clk) cnt_p <= cnt_p_nx; always @(negedge clk) cnt_n <= cnt_n_nx; endmodule // clk_div3
You can add reset signal to remove the initial statement!
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