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# Clock divider by 3 with 50% duty cycle?

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#### echo47

clock division by 3

Lots of confusion here, because we are kicking around different ideas, and explaining each-other's messages.

I don't like logic that relies on delays. I like the Xilinx application note that IanP suggested, however my favorite solution is a frequency multiplier based upon a DLL or PLL.

#### blanket

##### Junior Member level 3
how to design a 50% duty cycle clock

Haha...Ok, I agree. Let's give this topic a rest!

#### vipulsinha

##### Member level 2
33 % duty cycle counter design

Hi
U can use 2 flop johnson counter for the div by 3 module. As johnson counter counts for 2N-1 cycle where N is the no of flops.

#### appleleaf

##### Junior Member level 1
divide by 3 counter with 50% duty cycle

I think that using both edge of the input clock will be another soluation.

#### PitBull

##### Newbie level 5
50% duty cycle divide

I ve had this question before and there are a couple of replies on this site.
All credit to Satish B.

#### littlefield

##### Junior Member level 3
divide by three clock divider

hi
why should divide "XOR" by 3， then divide "divide3" by 2??????
WHY NOT divide "XOR" by 6 directly

when 0,1,2 ,the output is '0',
when 3,4,5 ,the output is '1',
it also have 50% duty cycle

echo47 said:
The "divide it by 3" can be just an ordinary two-bit counter that goes 0,1,2,0,1,2,...

After doing those steps, you would have signals like this. For the output to have 50% duty cycle, the input clock must also have 50% duty cycle.

##### Member level 5
clock divider 3

This a very good paper on clock dividers

#### jasmine25

##### Newbie
clock divider duty 50%

thank you very much .....buddy

maxsnail said:
Thanks. it is useful for me
nand_gates said:
Here is one more ckt in verilog!!
Code:
module clk_div3(clk,clk_out);
input clk;
output      clk_out;

reg [1:0]   cnt_p, cnt_n;
wire [1:0]   cnt_p_nx, cnt_n_nx;

initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;

endmodule // clk_div3

You can add reset signal to remove the initial statement!

#### aznsj

##### Newbie level 6
i got it , thanks a lot

#### urmish

##### Newbie level 5
Re: clk divider 3

the best way and glitch free way is mentioned here
ASIC Verification: Clock Dividers

For the lazy ones I have quoted the text below
The easiest way to create an odd divider with a 50% duty cycle is to generate two clocks at half the desired output frequency with a quadrature-phase relationship (constant 90° phase difference between the two clocks). You can then generate the output frequency by exclusive-ORing the two waveforms together. Because of the constant 90° phase offset, only one transition occurs at a time on the input of the exclusive-OR gate, effectively eliminating any glitches on the output waveform.

Let’s see how it works by taking an example where the REF_CLK is divided by 3.

Create a counter which is incremented on every rising edge of the input clock (REF_CLK) and the counter is reset to ZERO when the terminal count of counter reaches to (N-1). where N is odd number (3, 5, 7 and so on)

Take two toggle flip-flops and generate their enables as follows; T-FF1 is enabled when the counter reaches '0' and T-FF2 is enabled when the counter reaches (N/2)+1.

Output of T-FF1 is triggered on rising edge of REF_CLK and output of T-FF2 is triggered on the falling edge of REF_CLK.

The divide by N clock is derived by simply Ex-ORing both the output of T-FFs.

#### jai15

##### Newbie level 3
Can anyone re-upload the clock divider made easy pdf. I am not finding at any of the links..

jai

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### jai15

Points: 2

#### RodneySoul

##### Newbie level 1
Would this work? use a shift register that generates this pattern on the posedge: 100100100...

Delay this pattern by a half clock with a negedge flop, then OR the outputs together. You get a 50% duty cycle with no glitches.

Cannot use a FSM to generate the pattern since that can glitch.

So if I expand the sequence to show both posedge and negede of the clock:
shifter : 11000011000011...
delayNeg: 011000011000011..
OR gate : 111000111000111..

4-flops.

- - - Updated - - -

Maybe if FSM is gray coded then you can avoid glitches, so an FSM would be 2 flops + 1 flop = 3 flops.

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