jugemu1234
Newbie level 5
Hi all,
I've been working on CDR basics study. CDR is supposed to b useful because clock can b embeded. In fact however, many SERDES rx uses external ref clock generated in tx.
I think that ext clk incorporated with phase interpolation may help to deserialize less jittery manner relatively. But downside would b apparently one diff pair for clock must b distributed from tx to rx (this won't b problem if used local osc).
Can anybody suggest me if there is any other advantage to use ext ref clk in CDR system?
Thx in advance.
I've been working on CDR basics study. CDR is supposed to b useful because clock can b embeded. In fact however, many SERDES rx uses external ref clock generated in tx.
I think that ext clk incorporated with phase interpolation may help to deserialize less jittery manner relatively. But downside would b apparently one diff pair for clock must b distributed from tx to rx (this won't b problem if used local osc).
Can anybody suggest me if there is any other advantage to use ext ref clk in CDR system?
Thx in advance.