rsrinivas
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Hi all
I have a design with some 13 modules and the controller controls the 12 modules.
I have synthesised the netlist and is working fine but now my problem is like this
The inputs to the controller are clk and reset.
from the clk input to the controller the controller generates clk to all the modules.
The maximum operating speed of my core(1 module) was 100 MHz but when i
use all the modules the speed of operation goes beyond 300 Mhz.
this may be because DC has to be given directives like there are generated clk's in the design
now how do i solve this.
pls help
cheers
srinivas
I have a design with some 13 modules and the controller controls the 12 modules.
I have synthesised the netlist and is working fine but now my problem is like this
The inputs to the controller are clk and reset.
from the clk input to the controller the controller generates clk to all the modules.
The maximum operating speed of my core(1 module) was 100 MHz but when i
use all the modules the speed of operation goes beyond 300 Mhz.
this may be because DC has to be given directives like there are generated clk's in the design
now how do i solve this.
pls help
cheers
srinivas