Clearance error in Eagle

[keith1200rs]

I did look for a tutorial on 4 layer layout (Eagle or otherwise) but couldn't find one.

Your requirements are quite normal and not something that needs blind vias. You would normally on use blind & buried vias when it is unavoidable - because it costs more. One example would be where you have a BGA on both sides of a board. You could not put a via completely through the board because it would hit the other BGA pads.

But, a normal layout of 4, 6 or maybe 8 layers would simple have vias that go straight through the board from top to bottom. You can also connect to them on any layers inbetween. So, while you might only want to connect from layer 1 to 2, the via also exists on layers 15 and 16. It does waste a bit of space but that usually isn't much of an issue.

I usually find more problems with vias between layers 1&16 hitting tracks on the inner layers when the layout is dense and components on both side.

So, use a simple 4 layer build and put normal vias from 1 to 16, and connect to them on the inner layers as required.

If you name you inner layers the same as you GND and VCC nets then when you add a via from a GND or VCC pad it will automatically connect to the inner layer. You will need to do a 'ratsnest' command to remove the unrouted net.

I hope I am being clear.

Keith

 

[swapna2009]

Hello Keith,

Really many many thanks for that expalantion. It is really clear, I got it this time. Now I am uisng (1*2+15*16) layer setp. now I am not using blind vias. with the original via only I could connect it to inner layers.

I am not using netclasses.

again I came up with another question.
Here I have used four vias. one set of 2 for +VCC one is at Pin 7 of IC and one at +9V battery. Another set of 2 for -VCC one is at Pin 4 of IC and one at -9V battery.
Vias at batteries are not having traces with battery terminals. even when I use auto route there is no routing between them.

Here my question is; Is it normal if so, how can they pysically connected can you please give me a reasoning for that.

Keith , can you also look over my whole design and tell me if any mistake is there.

Here I have attached files which can explain my problem

Thank you very much,

Thanks,
-Swapna

 

[keith1200rs]

I am not quite sure I understand what your question is. You don't need vias for the batter terminals - they are through hole components and so automatically connect to the correct inner layers. If you look at the pads (after a "ratsnest" command) you will see the thermal reliefs on the inner layers where they are connected.

If you want to add extra vias to connect to GND or any other net then place a via with that name. If you just place a via (type VIA) then it will have a net name which is the next one in sequence and will be unconnected, unless you place the via directly on a net with another name. So, after placing a via, click on the "NAME" icon or type NAME and rename it to the net you want. Then it will automatically connect to that name if it can or create a ratsnest if it cannot.

Your via above G1 is already connected to -VCC through layer 15. There are no thermals - vias don't need them.

Keith.

 

[swapna2009]

Hello Keith,

Can you please help me out with my new problem.

I have created a component-2pin header in eagle library. which you can find in the follwing link

Digi-Key - 277-1273-ND (Manufacturer - 1725656)

I want to use them for battery clips,
I don't know where is the problem. those are not connecting to any other pins.

I was connecting them to both +VCC an d-VCC pins and ground of IC but that one looks idle in the board layout none of the trace is connected.

Here I am attaching created 2pin_header library component, schematic and board files.

Can you please look at it and let me know the mistake.

Thankyou very much,
-Swapna

 

[keith1200rs]

It doesn't connect because your wires don't quite meet the pins - they are off grid. Stick to the 0.1" grid on the schematic at all times.

Keith.

 

[swapna2009]

Hi keith,

I designed my whole circuit finally.... and I did auto route it, I am getting many dimension errors. I could not figure out what it is.

Here I have attached both schematic and board files of that circuit. Can you please check it once and let me know the solution.

Keith , I have few more questions,
1.which one we should prefer auto routing or manual routing???
2. In design is it better to have many traces like complicated paths or many vias?
3. can you please look at my routing in design and suggest me best routing tips..

Thanks a lot.
-Swapna.

 

[keith1200rs]

The key to a good layout is component placement. If that is not right then manual or auto routing will not give good results.

I almost always manually route. I can see circumstances where autorouting woud be useful (a lot of digital circuitry to route) and I have on occasion used it but I think if you do then you really need to get to know your autorouter and spend time setting it up. Similarly you need to set the characteristics of critical nets and power nets so the autorouter has more information to work with. For manually routing then you will already have the information in your head (I hope).

So,

1. manual for me
2. neither. For high frequency boards then you might want to minimise vias but then you also don't want the route between two points to be any longer than necessary either. Good placement minimises path length & vias. Extra layers can help to minimise vias e.g. if you route on a 4 layer board compared to a 2 layer then it should free up space to route on the main layers.
3. place components to follow the signal flow and place passives round the ICs to minimise the connection path length.

In your library parts make sure you label the pins 1,2,3 etc.

Place the origin of components in the centre, not at a corner.

4. don't use very fine grids. You board consists of mainly through hole components on a 0.1" pitch so make the main grid 0.05" not 0.01mm! You can make the secondary grid 0.025". I am sure I have said this before.

Keith.