clear a file in verilog

[nehat]

hi,
I amusing $fopenw and $fwrite for dealing with my filein my verilog code.
every time my code enters always@(posedge clk) block , i want to rewrite my file (not append to the end of the file),
in other words i want to clear my file and then write it again.

is there any way to clear a file in verilog???


please please answer me asap. i am going nuts!!

thank you in advance

 

[FvM]

Append versus rewrite is controlled by the $fopen type parameter, just read the Verilog specification completely, e.g. IEEE 1800-2012, 21.3.1 Opening and closing files