**************************************************************************
* DIGITAL SINGLE POLE LOW-PASS FILTER *
**************************************************************************
* Fosc=12.8MHz, Prescaler=64; ##T=50*Tms CT=50 *
* Input: AD3 (pin2) Range: $00-$FF *
* Sample rate=10ms *
* Filter parameters:b1=0.875;a0=0.125; F=1/a0=8; d=7.5 *
**************************************************************************
$nolist
$include 'Fr908QT2.asm'
$list
PERIOD EQU $01F4 ;Sample rate =10ms; (50*10=500=$01f4 ),
S EQU 3 ;Number of right shifts to divide by F=8
HAlFF EQU 4 ;Half of devisor F=8 (for rounding during division)
*VARIABLES
ORG RAM
INPUT RMB 1 ;X{n}
OUTPUT RMB 1 ;Y[n]
INCREMENT RMB 2 ;X[n] - Y[n-1]
SampleCNT RMB 1 ;Sample counter for testing only
*INITIALIZATION
ORG ROM
init RSP ;$FF-->SP
CLRA
CLR INPUT ;Clear registers
CLR OUTPUT
CLR INCREMENT
CLR INCREMENT+1
CLR SampleCNT
LDA $FFC0 ;adjusting frequency
STA $0038
MOV #$01,CONFIG1 ;cop disabled
MOV #$41,CONFIG2 ;RST-active in pin,IRQ-active in pin
CLRH ;clear H:X
CLRX
CLR prtA ;clear prtA
MOV #pA0.,DDRA ;set pA0 output,pA1-pA5 inputs
MOV #0,TSC0 ;clear TSC0
LDHX #PERIOD ;PERIOD -->TmodH & TmodL
STHX TmodH
MOV #%00010110,TSC ;clear TIMER,start TIMER,prescaler:64
********************************************************************************
MAIN BRCLR TOF,TSC,* ;wait for the end of PERIOD
BCLR TOF,TSC ;TOF reset
ReadADC MOV #3,ADSCR ;start ADC3
BRCLR COCO,ADSCR,* ;wait for ADC3 end
MOV ADR,INPUT ;ADR->INPUT
INC SampleCNT
Filtering JSR Filter
BRA MAIN
********************* DIGITAL LOW_PASS FILTER ************************************
Filter LDA INPUT ;Calculate (X[n] - Y[n-1])
SUB OUTPUT
STA INCREMENT+1
clc
LDA INCREMENT+1 ;Calculate (X[n]-Y[n-1])+halfF
ADD #HALFF ;(for rounding the result of division)
STA INCREMENT+1
LDA INCREMENT
ADC #0
STA INCREMENT
LDA #S ;division on F=8, by S=3 right shifts,
mf1 ASR INCREMENT
ROR INCREMENT+1
DBNZA mf1
LDA OUTPUT ;Calculate Y[n]=Y[n-1] + (X[n]-Y[n-1])/8
ADD INCREMENT+1
STA OUTPUT
RTS
************************************************************************************
ORG $FFFE ; Position to reset vector
FDB init ; Set start address
$nolist