Circuit for Clock Divide by 5 and 50 % duty cycle (urgent)

[spartanthewarrior]

divide by 5 circuit

Hi All,

Please help me it's urgent.................

 

[AdvaRes]

divide by 5

 

[arvkum02]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

The basic way to design is :

First design a normal divide by N (here N=5) or mod N counter .
Analyses all the waveforms from the flops O/P.
Take a waveform that is high for (N-1)/2 (here 2) clock cycles (over a period of N cycles).

Delay this waveform or flop o/p by half of the clock period (give this signal as an input to a -ve edge triggred flop , the o/p will be delayed by half clock period).

Add the delayed and non delayed signal you will get desired o/p.

Feel free to ask further.

Arvind

 

[koggestone]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

as suggested by arvkum02 in above reply , the steps are

1) generate straight forward div-by-5 with 40% duty cycle.
lets say its clkA.

2) feed this clkA to -ve edge triggerd flop . lets say the output is clkB.

3) required 50% duty cycle clk is OR of clkA and clkB.
clk50 = clkA | clkB;

Below is a pseudo code . u can use similar format for div-by-3/7/9/ etc ...

=========================

reg [2:0] count;
always @(posedge clk or negedge reset_n)
if (~reset_n)
count<=0;
else if (count == 3'd4)
count<=0;
else
count <=count+1;

assign clkA = count[1];

always@(negedge clk)
clkB <= clkA;

assign clk50 = clkA | clkB;

============================

In case , they ask u this question in interview ( Which 80% of time this will)
and u get hired , then Thank me (and arvkum2) in your Heart!!.

 

[rakko]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

start two counters (LFSR is better) at the same time, one running from positive edge of the clock and the other from negative. When the positive edge counter is 2 and negative edge one is 3, toggle your output, reset both counters, and repeat. works for divide by any number.

2-bit counters.

 

[simonsunsun]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

it's very help for me, thanks!

 

[senthilos]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

Hi Arvind,

What do you mean by 'Analyses all the waveforms from the flops O/P'? I didn't get that point straight.

The basic way to design is :

First design a normal divide by N (here N=5) or mod N counter .
Analyses all the waveforms from the flops O/P.
Take a waveform that is high for (N-1)/2 (here 2) clock cycles (over a period of N cycles).

Delay this waveform or flop o/p by half of the clock period (give this signal as an input to a -ve edge triggred flop , the o/p will be delayed by half clock period).

Add the delayed and non delayed signal you will get desired o/p.

Feel free to ask further.

Arvind

Added after 2 minutes:

Hi Koggestone,

In your verilog code shouldn't CLKA be computed as
assign clkA = ~(count[1] | count[2]);

as suggested by arvkum02 in above reply , the steps are

1) generate straight forward div-by-5 with 40% duty cycle.
lets say its clkA.

2) feed this clkA to -ve edge triggerd flop . lets say the output is clkB.

3) required 50% duty cycle clk is OR of clkA and clkB.
clk50 = clkA | clkB;

Below is a pseudo code . u can use similar format for div-by-3/7/9/ etc ...

=========================

reg [2:0] count;
always @(posedge clk or negedge reset_n)
if (~reset_n)
count<=0;
else if (count == 3'd4)
count<=0;
else
count <=count+1;

assign clkA = count[1];

always@(negedge clk)
clkB <= clkA;

assign clk50 = clkA | clkB;

============================

In case , they ask u this question in interview ( Which 80% of time this will)
and u get hired , then Thank me (and arvkum2) in your Heart!!.

 

[koggestone]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

Hi Koggestone,

In your verilog code shouldn't CLKA be computed as
assign clkA = ~(count[1] | count[2]);

clkA=count[1] is correct in my verilog code.

divide-by-5 count looks like
0 1 2 3 4 0 1 2 3 4 0 1 2 ...

in terms of binary
count[2] = 000010000100001......
count[1] = 001100011000110......
count[0] = 010100101001010......

u can see that count[1] is high for 2 out of 5 cycles (40% duty cycle)
clk50 will have 50% duty cycle

 

[mux_master]

Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

Interesting discussion. I had not had a need for an odd divide with 50/50 duty cycle before so had never considered this circuit design, so I took this opportunity to learn some more about it. I created a verilog module that can divide the input clock by 3,5,7 or 9, the design based on the discussion in this thread. Here is a link to it in case anyone may find it useful:
**broken link removed**

 

[bbulutlu]

module clkdiv(
input CLKIN,
output clkout
);
reg [2:0] counter1;
reg [2:0] counter2;
wire clkout1;
wire clkout2;

always @(posedge CLKIN)
if(counter1!=4) counter1 <= counter1+1;
else counter1 <= 0;

always @(negedge CLKIN)
if(counter2!=4) counter2 <= counter2+1;
else counter2 <= 0;

assign clkout1 = counter1[1];
assign clkout2 = counter2[1];
assign clkout = clkout1|clkout2;

endmodule

 

[morris_mano]

module clkdiv(
input CLKIN,
output clkout
);
reg [2:0] counter1;
reg [2:0] counter2;
wire clkout1;
wire clkout2;

always @(posedge CLKIN)
if(counter1!=4) counter1 <= counter1+1;
else counter1 <= 0;

always @(negedge CLKIN)
if(counter2!=4) counter2 <= counter2+1;
else counter2 <= 0;

assign clkout1 = counter1[1];
assign clkout2 = counter2[1];
assign clkout = clkout1|clkout2;

endmodule

Why use extra 3-bit counter2 reg when you can just do away with one bit by doing below:

always@(negedge CLKIN)
clkout2 <= clkout1;

 

[vka]

how is this code

https://technicalone.blogspot.in/2013/07/verilog-code-for-clock-divider.html