CIC filter design in VHDL

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Mkanimozhi

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cic filter vhdl

Hi,
i need to design the CIC decimation filter in VHDl for GSM frequency, i don't know nothing about CIC filter , if any one have detailed document for CIC filter design ,plz send it to my mail -id mkanimozhivlsi@gmail.com


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kanimozhi.M
 

cic vhdl

hi

just check xilinx website reference design cic filter, you can do it.

regards

kari
 

cic filter design

I have checked that document ya, but it is very simple, i need to know detail about the comb filter,how tos elect the sampling frequency, and decimation facotor and every thing..........

regards
Kanimozhi.M
 

vhdl cic filter

Hogenauers original paper introducing the CIC filter should be your basic literature. Also Uwe Meyer-Baeses book DSP with FPGA has a profound CIC chapter.
 

How to cascade the CIC's stages in the VHDL code? As I have tried for the example 5.3 in the UweMeyer Baese books pg192 n 199, the INTROCESS and the COMBROCESS, is that shows how they cascade?

I need to have more example on similar CIC decimator filter is there anyway to find? thanks for reply
 

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