CIC filter design in VHDL

[Mkanimozhi]

cic filter vhdl

Hi,
i need to design the CIC decimation filter in VHDl for GSM frequency, i don't know nothing about CIC filter , if any one have detailed document for CIC filter design ,plz send it to my mail -id mkanimozhivlsi@gmail.com


Regards
kanimozhi.M

 

[karikalan_t79]

cic vhdl

hi

just check xilinx website reference design cic filter, you can do it.

regards

kari

 

[mkanimozhivlsi]

cic filter design

I have checked that document ya, but it is very simple, i need to know detail about the comb filter,how tos elect the sampling frequency, and decimation facotor and every thing..........

regards
Kanimozhi.M

 

[FvM]

vhdl cic filter

Hogenauers original paper introducing the CIC filter should be your basic literature. Also Uwe Meyer-Baeses book DSP with FPGA has a profound CIC chapter.

 

[gsc1987]

How to cascade the CIC's stages in the VHDL code? As I have tried for the example 5.3 in the UweMeyer Baese books pg192 n 199, the INTROCESS and the COMBROCESS, is that shows how they cascade?

I need to have more example on similar CIC decimator filter is there anyway to find? thanks for reply

 

[gsc1987]

Doing CIC literature review.. @,@