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CIC Decimation Filter for 1-bit SD-Modulator

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bardia

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Dear all,

I want to design a CIC decimation filter for a 3rd-order sigma-delta modulator with single-bit quantization.

As we know, CIC filter need's 2's complement arithmetic. Let's assume I need 16 bits internal word length for correct operation.

Now my question is, do I need to convert my 1-bit unsigned quantized data (at the the modulator output) to the equivalent 16-bit 2's complement world length at the input of the CIC filter?

Which means 1b'0 to -1 = 16'hFFFF, and 1'b1 to +1 = 16'h0001.

Thanks for your help.
 

fpgaengineer

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Yes and you have to do this in a continous way, meaning accumulating the 1Bit-Values to a data strea, You do not necessarily have to do this for 63556 Bits because this filter is a filter with a square window which's filtering effect should better be achieved by the CIC. On the other hand, it is not necessary to process with full bandwidth and apply only two values (0, 65535) for the filter input. A simple accumulation performed by a FIR-filter in front of the CIC ist mostly choosen.

You can apply a preaccumulation using:

samples 0..15 for word 1
samples 1..16 for word 2
...
samples 16 to 31 word 17

and so on.

Again, this applies when you want to process with data input speed. If you need only much less, than 1/16 of the input speed (refers to you nyquist freq) than you can stay with each 16th sample as one would assume to process.

Several CIC-filters do have this SER/PAR-Method included, some have not.
 
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