Feb 22, 2013 #1 S sarmad88 Junior Member level 2 Joined Feb 12, 2013 Messages 20 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,474 please help me My design when configration it on the FPGA and read the results through the chipscope i do not show the correct results Note that the results in post place and rout simulation are correct
please help me My design when configration it on the FPGA and read the results through the chipscope i do not show the correct results Note that the results in post place and rout simulation are correct
Feb 23, 2013 #2 joelby Full Member level 4 Joined Jun 6, 2011 Messages 196 Helped 66 Reputation 130 Reaction score 64 Trophy points 1,308 Activity points 2,644 Is timing constrained properly in your design? Are you meeting timing?