asicdesigner2014
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chipscope PRO analyzer: Waiting for Core to be armed, slow or stopped clock
Hi
I'm trying to observe signals on waveform window in chipscope pro analyzer for viretex 7 FPGA on VC707 board. I get the message that "Waiting for Core to be armed, slow or stopped clock".
FYI, I've hooked up the design clock port *clk_BUFGP onto board ocsillator 200mhz SYSCLK_P pin at FPGA pin E19 . I have set the trigger port as the Reset signal of my design which I've connected to user DIP switch SW2 and set the clock, reset on data ports for observation in waveform.
Kindly advise how to resolve the above error message and how to view 200Mhz system clock in waveform
Thanks
Hi
I'm trying to observe signals on waveform window in chipscope pro analyzer for viretex 7 FPGA on VC707 board. I get the message that "Waiting for Core to be armed, slow or stopped clock".
FYI, I've hooked up the design clock port *clk_BUFGP onto board ocsillator 200mhz SYSCLK_P pin at FPGA pin E19 . I have set the trigger port as the Reset signal of my design which I've connected to user DIP switch SW2 and set the clock, reset on data ports for observation in waveform.
Kindly advise how to resolve the above error message and how to view 200Mhz system clock in waveform
Thanks
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