Re: FET Design question
Here is a typical FET switch. When the bipolar is turned on, +5V is being applied to the cathode of the diode and so the diode is off. R1 shorts the G and S of the FET, so the FET will be on and the signal can pass through it. With the bipolar off, the gate of the FET is pulled to -12V and so the FET is forced off, the signal not being able to pass through it.
To ensure the switch operates properly, there are restrictions on the input voltage range: the FET must stay on if the bipolar is on. So the maximum input voltage is about 5.6V. Anything higher and the gate appears negative to the source and begins to turn off the FET. Also, the FET must stay off when the bipolar is off. That means that the input voltage cannot go so negative that the FET can turn on. The 4393 has a turnoff voltage of about -3V, but other FETs can have voltages of -10V. So, to guarantee the fet stays off, the source cannot go to less than -12+3V=-9V, for the 2N4393, or lower than -6V for a 2N4392. So the input voltage can vary between about +/-5V without any problem.