Maybe the frequency at which you are switching the pink color current is close to the -3 dB cut-off frequency of the mirrored pmos transistor (right side up) together with the driver nmos transistor having input DN.
Maybe due to the large output resistance of that pmos transistor, it is having a smaller bandwidth. I think if you increase the W/L ratios of all the transistors proportionately by keeping them in saturation a larger current will flow through them leading to smaller output resistance of the pmos transistor (1/λID).
But I cant tell what your power budget is?
The cut-off frequency of a simple inverter in UMC 180nm technology biased in saturation region can be up to 2 GHz. You can reach higher frequencies like 2.4 GHz in 180nm by using inductors as loads. One such example is RF Low Noise Amplifiers. Your operating frequency is 5 GHz.
The pmos transistor in the upper right corner of the circuit is acting as a current-source load and has a high output resistance. Maybe its bandwidth cannot be more than 500 MHz.
My opinion is you can either use inductors in your design or maybe go to lower technology nodes like 90nm...
However that is my opinion!! I may be wrong. Maybe you should wait for any other responses to this topic!!
how can i test my CMOS technology cut off frequency??(speed limit) in cadence
Suppose you want to want to find out the bandwidth of a CS amplifier with resistive load.
Set a nmos transistor with W/L=2u/1u. Add a load resistance of 1K. Now vary the gate voltage of the nmos from 0 to Vdd. Plot the output voltage. You'll get a curve similar to an inverter transfer characteristics.
Generally we want to set the bias point for an amplifier for maximum gain. So you can take the derivative of the output voltage curve and find out the input voltage for maximum value of the derivative (derivative of Vout vs Vin = Gain of the amplifier).
Now add a dc voltage to the input whose dc magnitude is the value of input voltage for maximum gain. Add ac magnitude = 1V.
Now do the ac analysis, vary the frequency from 1K to 100G.
Go to results -> direct plot -> ac dB20 -> select the output node and escape.
You'll get the gain magnitude plot in dB scale. Suppose the gain at 1K is 18 dB. Then the cut-off frequency or 3 dB bandwidth will be the frequency where the gain falls to (18-3)=15 dB.
I hope this helped.
I guess the average voltage for UP signal is 1.3 V. So add a dc source whose dc magnitude is 1.3 V and ac magnitude 1 V.
Then do the ac analysis. Vary the frequency from 1K to 100G. Plot the ac dB20 of drain voltage of the upper right pmos transistor.
If it dosen't show anything, then maybe you have to disconnect the voltage source that have been connected at the output node.
Then do the analysis once again.
I guess the average voltage for UP signal is 1.3 V. So add a dc source whose dc magnitude is 1.3 V and ac magnitude 1 V.
Then do the ac analysis. Vary the frequency from 1K to 100G. Plot the ac dB20 of drain voltage of the upper right pmos transistor.
If it dosen't show anything, then maybe you have to disconnect the voltage source that have been connected at the output node.
Then do the analysis once again.
No, this is not the correct graph!!
Some of the transistors may not be in saturation region, they might be in linear region.
Give 1.3V in the UP signal. Give appropriate dc voltage to DN signal. Do dc analysis. See if all the transistors are in saturation.
Note that the transistors should show "region 2" after dc analysis if they are in saturation.
Found a paper where they are using varactors and applying differential control voltage to the varactor network.
"A 38 GHz accumulation MOS differentially tuned VCO design in 0.18µm CMOS" - Carr, Frank
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