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Charge distribution AD Converter

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snoop835

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Hi Guys,

I am designing 8-bit SAR Converter based on the following journal. (see attachment file)

Can someone throw me some light on how to decide the capacitor value for the sample-hold circuit. Is there any good reference or design guidelines for this circuit?

Cheers!
 

the value of the capactor can be several pf,you should simulate your circuit.
and you also consider the parasitic capactor .

regards
 

the main problem is KT/C noise.
pay attention to it not bigger than 1/3 of least bits
 

For a mere 8-bit ADC, kT/C noise should not be an issue. You should pick it based on matching. As a second thought, even matching should not be an issue here since it is again, an 8-bit converter.
 

several pf is enough for you to realize a 8bit resolution. I think the key are the cap mismatch and the offset of your comparator.
 

i want to design a 10bit 50khz low power sar adc,can anyone give me some advice or reference ?
 

you can refer to the book from DAvid Johns & ken Martin. it was discussing the charge distribution ADC.
 

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