Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Channel formation in FD SOI

Not open for further replies.

Anand Cool B

Member level 2
Jan 13, 2014
Reaction score
Trophy points
Activity points
Hi all,
Can anyone please say me how a channel is formed in full depleted silicon on insulator or Fully depleted Finfet.How the channel is formed without the substrate.

Thanking You

That's one of the tricky bits about FDSOI. The body can
assume a range of potentials and can be charge pumped,
although at DC the B-S diode conduction and D-B leakage
currents will sum to "something".

Usual MOS equations refer to Vgs, not Vgb although the
body potential does have a significant role.

Fully depleted seems to be taken to mean more, by people,
than it does. Such as assuming the body is always depleted.
Fully depleted means that -at Vgs=0- the body is depleted
all the way back to the BOX. But once you enter weak
inversion the body pocket is now shielded from the gate
by the channel / inversion charge sheet, and can assume
any potential it likes, until Vgs is driven so high that the
body fully inverts instead (and this is one of the great
attractions of FDSOI, that you can get a stronger channel
by crowding it to the surface, than letting it taper into
the substrate).


    Points: 2
    Helpful Answer Positive Rating
So do u mean the electrons for the channel formation are provided by the source in a SOI.(Do u mean the weak inversion and the strong inversion will be initiated by the source and gate voltages).

But in CMOS the bulk voltage affects Vt so in CMOS and PDSOI bulk plays a major role in creating the channel.As the Vsb varies Vt varies.So my question is without the bulk how is the channel formed and how is the Vt defined.

Thank you

Electrons in the inversion layer are always provided by source or drain n+ heavily doped regions - irrespective of whether this is bulk device, fully- or partially-depleted SOI - assuming there is n+ region in proximity with the gate. (without n+ regions, electrons are provided through thermal generation in the depletion layer under the gate - but this is a very slow process).
Electrons are not provided by the substrate, which is usually doped opposite type to the device type (p-substrate or bulk in the case of nMOSFET).

The mechanism of channel formation is simple, in principle - with positive voltage applied to the gate (for nMOSFET case), the potential barrier for electrons, from source to channel, is lowered, until electrons start filling in the potential well - this way, the inversion layer is formed.
  • Like
Reactions: Bhag123 and erikl


    Points: 2
    Helpful Answer Positive Rating


    Points: 2
    Helpful Answer Positive Rating
Then can you explain how Vt varies with Vsb in nMOSFET,If according to you bulk is not playing any role in channel formation.

He did not say the bulk plays no role. He said it is not the
primary source (that's source, son) of channel charge.
Jacking the bulk potential around alters how much charge
must be put from the source, to bring the surface to
inversion. And this potential can vary a lot with defects,
dopant distribution and history.


    Points: 2
    Helpful Answer Positive Rating
Yes, thanks dick_freebird for explaining this.

We can think of some analogies here.
If you open a faucet, the water will flow.
The water is not supplied by the faucet - it is supplied by the pipes (and by water distribution system).
But the flow of water is controlled by the faucet.

Same thing in MOSFET - the electrons in MOSFET are supplied by source (or source and drain, if Vds is small), but the concentration of electrons in the channel is controlled by the Vbs - substrate/body voltage (and, of course, by Vgs - gate voltage).
Electron concentration is a primary, threshold voltage is a secondary (derivative) parameter.


Interesting discussion and good points. I can maybe add some input also.

(Ultra-thin body and box) FD-SOI is what I have had experience with. The channel below the gate works just as a (bulk) MOSFET. For example, in an NMOS FD-SOI, if you apply a large enough Vg (e.g. Vg>*Vth), then the channel inverts in the body. The body is between the gate and the box. The body is very thin ... so the depletion layer is fully below it (and thus there is no floating body effects).

To change the Vth of the transistor, apply a voltage on the "back-side" of the box. This back-gate biasing acts like another gate. In fact, you can think of FD-SOI as having two gates: the top gate (i.e. Vg) and the back-gate. The back-gate bias voltage applied can be much larger than 0.6 V since there are not any diodes to worry about. The ability to have a large back-gate bias voltage (between the thin box and channel) makes for excellent control of Vth (e.g. 100s of mV change). It is a very useful tool!

CMP, a manufacturer in Europe of FD-SOI, has excellent resources explaining how fd-soi works:
(see "News and Events" section for excellent presentations)

*Vth=threshold voltage

Cheers :bsdetector:,


    Points: 2
    Helpful Answer Positive Rating
You do not necessarily change the front VT faster than you invert the
back interface; this depends greatly on the BOX attributes. I have
worked in a technology which was claimed to be fully depleted (and
may have been at Vgs=0) but manifested awful kink behaviors when
you got above Vgs=0. It was on the thicker end of what people say
is the range for full depletion.

The back interface is often an inferior oxide chemistry with more
noise and lower subthreshold slope, which you want to just shut
up. Maybe digital (with no care for phase noise / jitter) can pick
up a speed bonus by lowering effective VT, at the cost of leakage,
but most analog designers will be sorry they tried the trick. Not
to mention this is a global actor (handle bias) and prone to more
noise injection from outside and/or more noise coupling inside,
if made not-stiff relative to signal ground.


>but manifested awful kink behaviors when you got above Vgs=0.
Wow yeah that would be awful. So far I have not seen any kink effects due to the floating body (after a lot of sweeps and measurements). The IV curves are pretty ok even up to the nominal voltage.

I have built a number of digital blocks and some analog with a newer fd-soi. The analog blocks worked surprisingly well. The ability to adjust Vth was a big bonus for improving the conductance of the switches. But yeah ... I had limitations with leakage. No matter how good the best current technology is, a Vth at 0.1 V still gives too much leakage. Overall, the newer fd-soi processes seem to be rid of most previous problems (floating body, breakdowns, bjt, etc). I am curious to see how far fd-soi scales cost-efficiently.

freebird - Have you seen GlobalFoundries new 22 nm fd-soi?
I like the idea that they have tweaked processes for analog, low leakage, etc.


Not open for further replies.

Part and Inventory Search

Welcome to