By just keeping the simulation running.when it it losing so much ram?
You have to compile all the stuff under ./project_folder/component. The Actel and work directories have all the IP HDL that you generate in the Libero tools. You also have to make sure you compile the appropriate device library as you can't use the pre-compiled ones.I am using Microsemi Libero SoC 12.3 tool suite. With it comes ModelSim ME Pro 2019.2.
But I cannot run overnight simulations with this ModelSim ver as it loses memory @0.1MB/sec. It is the 32bit version and after >4GB utilization, ModelSim crashes.
Problem has been reported to Microsemi.
Now I also have a ModelSim DE-64 10.5 license and my intention is to use this instead of the shipped ModelSim version.
I have read the Microsemi docu modelsim_se_pe_libero_soc_ug.pdf but it speaks only about using ModelSim SE/PE or QuestaSim. I am not sure if I can use the ModelSim-DE version seamlessly.
Nevertheless I have been successful to launch the ModelSim DE version from Libero.
I have used the tool generated run.do file and have manually run the vlib, vmap and vlog/vcom commands inside the required directory (after deleting the previously generated ones). But I get errors during the DO file compilation. Some block designs and FIFOs throws errors. I never had these errors when the default ver of ModelSim was run using the same DO file.
So the question is, do I need to compile some other libraries?
Am I missing something?
I agree.If you have access to DE you should use it instead of the ME.
vsim -L PolarFire -L presynth -L COREAXI4DMACONTROLLER_LIB -L COREAHBLITE_LIB -L COREAHBTOAPB3_LIB -L COREAXITOAHBL_LIB -L COREAPB3_LIB -L CORESYSSERVICES_PF_LIB -L COREGPIO_LIB -L COREJTAGDEBUG_LIB -L CORERISCV_AXI4_LIB -L COREUARTAPB_LIB -L CORERESET_PF_LIB -L COREAHBLTOAXI_LIB -L COREFIFO_LIB -t 1ps presynth.gl6_pf_tb
do "wave.do"
run 1000ms
#In the Transcript window at the ModelSim or QuestaSim command prompt, change to the
#Microsemi folder (needs to be created)
#vlib - Create the folders to store the compiled libraries
#vmap - Map the simulation library location to the simulation library name
#vlog/vcom - Compile the simulation libraries from the Verilog/VHDL sources
mkdir Microsemi
cd Microsemi
vlib polarfire
vlib smartfusion2
vmap smartfusion2 C:/modelsim_dlx64_10.5/Microsemi/smartfusion2
vmap polarfire C:/modelsim_dlx64_10.5/Microsemi/polarfire
vlog -work smartfusion2 "C:/Microsemi/Libero_SoC_v12.2/Designer/lib/vlog/smartfusion2.v"
vlog -work polarfire "C:/Microsemi/Libero_SoC_v12.2/Designer/lib/vlog/polarfire.v"
Should be "the steps required to compile the libraries in order to run a non-bundled ModelSim version."the steps required to run a non-bundled ModelSim version.
Some block designs and FIFOs throws errors. I never had these errors when the default ver of ModelSim was run using the same DO file.
So the question is, do I need to compile some other libraries?
Am I missing something?
I am sure the tool generated DO file is taking care about them. It is attached.You never mentioned if you compiled all the files in the <libero_project>/components directories. That is where it stores all the FIFO and other IP generated by Libero.
No it has been generated from scratch. Some Microsemi IP cores have been used and the others are custom VHDL modules.Also is this a design being ported to Polarfire from another device family?
Thanks for the suggestions till now. I didn't provide the sim logs or DO file in order to keep it less complicated while I wanted to convey the problem as clearly as possible.I think I will stop here, I'm just making a lot of guesses as I have none of the errors or transcript information from modelsim or any other information on your project. At minimum having the Libero project file to see where all the files in the project are located and expanding the hierarchy view would allow you to see if any files are missing.
This is a good pointer. I will now explain what exactly fails.According to the PolarFire MLG that primitive IOD doesn't exist, which makes me think you either have IP ported from another family or you have a custom IOD module that hasn't been compiled into the design. Maybe you could try using a file search and look for "IOD" and see if there are any files with that as a module/entity name.
# ** Error: (vsim-3033) C:/Microsemi/Libero_SoC_v12.3/Designer/lib/vlog/polarfire.v(36064): Instantiation of 'iog_dlycntl' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /gl6_pf_tb/gl6_pf_0/amba_sys/CCC_0/PF_CCC_C0_0/pll_inst_0/u_delay/u_delay File: C:/Microsemi/Libero_SoC_v12.3/Designer/lib/vlog/polarfire.v
# Searched libraries:
# C:/modelsim_dlx64_10.5/Microsemi/polarfire
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/presynth
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREAXI4DMACONTROLLER_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/component/Actel/DirectCore/CoreAHBLite/5.4.102/mti/user_vhdl/COREAHBLITE_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREAHBTOAPB3_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREAXITOAHBL_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREAPB3_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/CORESYSSERVICES_PF_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREGPIO_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREJTAGDEBUG_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/CORERISCV_AXI4_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREUARTAPB_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/CORERESET_PF_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREAHBLTOAXI_LIB
# D:/work/fpga_gl6/gl6_pf_12_2/simulation/COREFIFO_LIB
Two tickets have been logged at Microsemi last week:
1. Provide pre-compiled libraries for DE-64 ver.
2. They have also acknowledged the ModelSim ME 2019.2 memory leak issue.
You shouldn't be asking for a pre-compiled library you should be requesting the source file that contains the missing module. For modelsim the library database is tied to the version.
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