So basically - you need to change something from xilinx - you have to re-build it from the GUI.
You could just instantiate the primitives for the RAM/FIFO in your own wrapper and then expose any/all generics.
Why wouldn't it work for a FIFO?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 U0 : fifo_generator_v13_1_4 GENERIC MAP ( C_COMMON_CLOCK => 0, C_SELECT_XPM => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 74, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 74, C_ENABLE_RLOCS => 0, C_FAMILY => "kintexu", C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 2, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 2, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 0, C_PRELOAD_REGS => 1, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 4, C_PROG_EMPTY_THRESH_NEGATE_VAL => 5, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 60, C_PROG_FULL_THRESH_NEGATE_VAL => 59, C_PROG_FULL_TYPE => 1, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_EN_SAFETY_CKT => 0, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "512x72", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "512x72", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 1, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => '0', rst => rst, srst => '0', wr_clk => wr_clk, wr_rst => '0', rd_clk => rd_clk, rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, prog_full => prog_full, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) );
No it is not...But is it the only reason??Because Xilinx Code isnt the easiest to decipher. And theres no documentation.
Xilinx really should fix the RAM/FIFO cores. These are cases where you don't need coregen in 90% of cases. I've seen custom workarounds to this that resulted in buggy designs. (mainly broken assumptions about flags due to the custom designs)
And the best part is SystemVerilog 2005. It has a fifo/queue data type that had a comment that the type wasn't specifically intended for synthesis but there was no reason it couldn't be synthesizable. So 12 years ago we almost had a basic type for what Xilinx thinks we only want to customize with a GUI.
They Way vivado works, it tends to give you a netlist for your IP Catalog files. And in vivado now its all in the .xci files, that have to be extracted.
Xilinx has no paramterisable stuff like Altera. They are starting to open up a bit (see this https://www.xilinx.com/support/docu...x2016_1/ug974-vivado-ultrascale-libraries.pdf ) , but currently it's only rams and synchronisers. No FIFOs or any of the other Altera handy IP.
Basically, they do this to lock you in hard to their tools an make your life harder.
They will even get sniffy in the forums when you ask for altera equivolents.
So basically - you need to change something from xilinx - you have to re-build it from the GUI.
I currently have a AXI register stage where different parts of the pipeline need different number of TUSER bits. I just generate it with a wide tuser, and leave the bits I dont need disconnected.
Good news,
Seems like the newer XPM constructs DO support FIFOs. They can be accessed through "Language Templates" in Vivado...
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FIFO_SYNC_MACRO_inst : FIFO_SYNC_MACRO generic map ( DEVICE => "7SERIES", -- Target Device: "VIRTEX5, "VIRTEX6", "7SERIES" ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold DATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb") FIFO_SIZE => "18Kb") -- Target BRAM, "18Kb" or "36Kb" port map ( ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output almost empty ALMOSTFULL => ALMOSTFULL, -- 1-bit output almost full DO => DO, -- Output data, width defined by DATA_WIDTH parameter EMPTY => EMPTY, -- 1-bit output empty FULL => FULL, -- 1-bit output full RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth RDERR => RDERR, -- 1-bit output read error WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth WRERR => WRERR, -- 1-bit output write error CLK => CLK, -- 1-bit input clock DI => DI, -- Input data, width defined by DATA_WIDTH parameter RDEN => RDEN, -- 1-bit input read enable RST => RST, -- 1-bit input reset WREN => WREN -- 1-bit input write enable ); -- End of FIFO_SYNC_MACRO_inst instantiation
But the XPM FIFO is...That is the macro to use a single BRAM as a FIFO. ITs not a generic FIFO that could use multiple BRAMs.
-- XPM_FIFO instantiation template for Asynchronous FIFO configurations
-- Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation
-- =======================================================================================================================
--
-- Parameter usage table, organized as follows:
-- +---------------------------------------------------------------------------------------------------------------------+
-- | Parameter name | Data type | Restrictions, if applicable |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Description |
-- +---------------------------------------------------------------------------------------------------------------------+
-- +---------------------------------------------------------------------------------------------------------------------+
-- | FIFO_MEMORY_TYPE | String | Must be "auto", "block", "distributed" or "ultra" |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Designate the fifo memory primitive (resource type) to use: |
-- | "auto": Allow Vivado Synthesis to choose |
-- | "block": Block RAM FIFO |
-- | "distributed": Distributed RAM FIFO |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | FIFO_WRITE_DEPTH | Integer | Must be between 16 and 4194304 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Defines the FIFO Write Depth, must be power of two |
-- | In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH-1 |
-- | In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+1 |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | RELATED_CLOCKS | Integer | Must be 0 or 1 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | WRITE_DATA_WIDTH | Integer | Must be between 1 and 4096 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Defines the width of the write data port, din |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | WR_DATA_COUNT_WIDTH | Integer | Must be between 1 and log2(FIFO_WRITE_DEPTH)+1 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies the width of wr_data_count |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | READ_MODE | String | Must be "std" or "fwft" |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | "std": standard read mode |
-- | "fwft": First-Word-Fall-Through read mode |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | FIFO_READ_LATENCY | Integer | Must be >= 0 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Number of output register stages in the read data path |
-- | If READ_MODE = "fwft", then the only applicable value is 0. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | FULL_RESET_VALUE | Integer | Must be 0 or 1 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Sets FULL and PROG_FULL to FULL_RESET_VALUE during reset |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | READ_DATA_WIDTH | Integer | Must be between >= 1 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Defines the width of the read data port, dout |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | RD_DATA_COUNT_WIDTH | Integer | Must be between 1 and log2(FIFO_READ_DEPTH)+1 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies the width of rd_data_count |
-- | FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | CDC_SYNC_STAGES | Integer | Must be between 2 to 8 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies the number of synchronization stages on the CDC path |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | ECC_MODE | String | Must be "no_ecc" or "en_ecc" |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | "no_ecc" : Disables ECC |
-- | "en_ecc" : Enables both ECC Encoder and Decoder |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | PROG_FULL_THRESH | Integer | Must be between "Min_Value" and "Max_Value" |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. |
-- | Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))+CDC_SYNC_STAGES |
-- | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) |
-- | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1 |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | PROG_EMPTY_THRESH | Integer | Must be between "Min_Value" and "Max_Value" |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted |
-- | Min_Value = 3 + (READ_MODE_VAL*2) |
-- | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2) |
-- | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1 |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | DOUT_RESET_VALUE | String | Must be >="0". Valid hexa decimal value |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Reset value of read data path. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | WAKEUP_TIME | Integer | Must be 0 or 2 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | 0 : Disable sleep. |
-- | 2 : Use Sleep Pin. |
-- +---------------------------------------------------------------------------------------------------------------------+
--
-- Port usage table, organized as follows:
-- +---------------------------------------------------------------------------------------------------------------------+
-- | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Description |
-- +---------------------------------------------------------------------------------------------------------------------+
-- +---------------------------------------------------------------------------------------------------------------------+
-- | sleep | Input | 1 | | Active-high | Tie to 1'b0 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode. |
-- | Synchronous to the slower of wr_clk and rd_clk. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | rst | Input | 1 | wr_clk | Active-high | Required |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | wr_clk | Input | 1 | | Rising edge | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Write clock: Used for write operation. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | wr_en | Input | 1 | wr_clk | Active-high | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | din | Input | WRITE_DATA_WIDTH | wr_clk | | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Write Data: The input data bus used when writing the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | full | Output | 1 | wr_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Full Flag: When asserted, this signal indicates that the FIFO is full. |
-- | Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive |
-- | to the contents of the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | overflow | Output | 1 | wr_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, |
-- | because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | wr_rst_busy | Output | 1 | wr_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | rd_clk | Input | 1 | | Rising edge | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Read clock: Used for read operation. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | rd_en | Input | 1 | rd_clk | Active-high | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | dout | Output | READ_DATA_WIDTH | rd_clk | | Required |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Read Data: The output data bus is driven when reading the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | empty | Output | 1 | rd_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Empty Flag: When asserted, this signal indicates that the FIFO is empty. |
-- | Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | underflow | Output | 1 | rd_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected |
-- | because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | rd_rst_busy | Output | 1 | rd_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | prog_full | Output | 1 | wr_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal |
-- | to the programmable full threshold value. |
-- | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Write Data Count: This bus indicates the number of words written into the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | prog_empty | Output | 1 | rd_clk | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal |
-- | to the programmable empty threshold value. |
-- | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | rd_data_count | Output | RD_DATA_COUNT_WIDTH | rd_clk | | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Read Data Count: This bus indicates the number of words read from the FIFO. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | injectsbiterr | Intput | 1 | | Active-high | Tie to 1'b0 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or |
-- | built-in FIFO macros. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | injectdbiterr | Intput | 1 | | Active-high | Tie to 1'b0 |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or |
-- | built-in FIFO macros. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | sbiterr | Output | 1 | | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. |
-- +---------------------------------------------------------------------------------------------------------------------+
-- | dbiterr | Output | 1 | | Active-high | Leave open |
-- |---------------------------------------------------------------------------------------------------------------------|
-- | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.|
-- +---------------------------------------------------------------------------------------------------------------------+
-- Set generic values and connect ports to instantiate an XPM_FIFO Asynchronous configuration
-- xpm_fifo_async :
-- VHDL :
-- component : In order to incorporate this function into the design, the following component declaration
-- declaration : needs to be placed in the architecture body of the design code.
-- code :
-- xpm_fifo_async : In order to incorporate this function into the design, the following component instantiation
-- VHDL : needs to be placed in the architecture body of the design code. The default values for the
-- component : generics may be changed to meet design requirements. The instance name (xpm_fifo_async_inst)
-- instantiation : and/or the port declarations after the "=>" declaration may be changed to properly reference
-- code : and connect this function to the design. All inputs and outputs must be connected, unless
-- : otherwise specified.
-- Copy the following two statements and paste them before the Entity declaration, unless they already exist.
Library xpm;
use xpm.vcomponents.all;
-- <--Cut the following instance declaration and paste it into the architecture statement part of the design-->
-- xpm_fifo_async: Asynchronous FIFO
-- Xilinx Parameterized Macro, Version 2017.2
xpm_fifo_async_inst : xpm_fifo_async
generic map (
FIFO_MEMORY_TYPE => "auto", --string; "auto", "block", or "distributed";
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
RELATED_CLOCKS => 0, --positive integer; 0 or 1
FIFO_WRITE_DEPTH => 2048, --positive integer
WRITE_DATA_WIDTH => 32, --positive integer
WR_DATA_COUNT_WIDTH => 12, --positive integer
PROG_FULL_THRESH => 10, --positive integer
FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
READ_MODE => "std", --string; "std" or "fwft";
FIFO_READ_LATENCY => 1, --positive integer;
READ_DATA_WIDTH => 32, --positive integer
RD_DATA_COUNT_WIDTH => 12, --positive integer
PROG_EMPTY_THRESH => 10, --positive integer
DOUT_RESET_VALUE => "0", --string
CDC_SYNC_STAGES => 2, --positive integer
WAKEUP_TIME => 0 --positive integer; 0 or 2;
)
port map (
sleep => '0',
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
overflow => overflow,
wr_rst_busy => wr_rst_busy,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty,
underflow => underflow,
rd_rst_busy => rd_rst_busy,
prog_full => prog_full,
wr_data_count => wr_data_count,
prog_empty => prog_empty,
rd_data_count => rd_data_count,
injectsbiterr => '0',
injectdbiterr => '0',
sbiterr => open,
dbiterr => open
);
-- End of xpm_fifo_async_inst instance declaration
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