changes to complement every three clock pulse

[julian403]

Hello, I have to do the next circuit for school.

Perform circuit having a 4-bit state, which change to complement
every three clock pulses.

I do not know what to do. I think i must use FF but how? or maybe there is a counter like Johnson which do it.

Thanks.

 

[harpv]

So the output of the circuit toggles every three cycles? Are you sure its mentioned to make a 4-bit state or 4 state logic, just curious.

Yes you should use flip-flops. And a counter as you rightly guessed. Johnson counter or normal counter also can be used.

I suggest you should draw a state transition table to understand what's happening in the circuit in every cycle. From this it'll be easier to build the logic.

To visualize the circuit behavior a timing diagram also can be handy.

 

[julian403]

Ok, for example I can make a synchronous counter, using the true table and then karnaught to get the gates. But, my problem it's the true table, which has 16 numbers (0-15). For example, the state 0000, I do not know what number is next which can be any but not 1111.

 

[ads-ee]

4-bit state information, but only 6 possible states are required to generate the output?
I don't quite understand why the problem was stated this way. Maybe the toggle output is one of the 4-bits of state information?

Optimizing I would have made the output one of the state bits (only using 3 registers):
000 | 0
001 | 0
011 | 0
111 | 1
110 | 1
100 | 1 -> go back to 000
010 | x
101 | x
Therefore the output is the same as the upper state bit.

if you coded it with straight binary you would probably want another register hold the toggle output (3 state registers, 1 toggle output register):
000 | 0
001 | 0
010 | 0
011 | 1
100 | 1
101 | 1 -> go back to 000
110 | x
111 | x

 

[julian403]

No, the circuit has 4 bit output state and every 3 clock pulse the output must be the first number's complementary. If I do a johnson counter, every 2 clock pulse there is the completary number.

 

[FvM]

You can take two different approaches:

- write an arbitray sequence of a four-bit signal that fulfills the given specification. (the complement thing, it must have a length of 6, all six states must be unique). Design the logic that generates the sequence (sketch carnaugh diagram, perform logic minimization).

- try to design a logic circuit that achieves a sequence with the said properties with minimal logic effort.

If you can't guess a solution for 2, implement 1.

 

[ads-ee]

No, the circuit has 4 bit output state and every 3 clock pulse the output must be the first number's complementary. If I do a johnson counter, every 2 clock pulse there is the completary number.

Sorry, I completely misinterpreted your description, I thought you wanted to toggle (i.e. complement) a signal. I guess I'm too used to trying to figure out what non-native English speakers are trying to convey.

So you want to do something like this, a one's complement for output every third clock output? (repeating after 6 clock cycles)
0000 | 0001
0001 | 0010
0010 | 1111
1111 | 1110
1110 | 1101
1101 | 0000

Or are you looking for something that complements the output of a 4-bit counter after 3 clock cycles?
0000 | 0010
0001 | 0001
0010 | 0000
0011 | 1111 <= complement of 0000 delayed three clocks
0100 | 1110
0101 | 1101
0110 | 1100
0111 | 1011
1000 | 1010
1001 | 1001
1010 | 1000
1011 | 0111
1100 | 0110
1101 | 0101
1110 | 0100
1111 | 0011

I'm not sure either of these are what you are asking.