library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity passwd is
port (
clk : in std_logic;
rst_n : in std_logic;
data : in std_logic_vector(7 downto 0);
start : in std_logic;
pass_wd : out std_logic_vector(7 downto 0));
end passwd;
architecture behave of passwd is
signal pass_word : std_logic_vector(7 downto 0) := to_stdlogicvector(x"AB");
signal pass_cnt : std_logic_vector(7 downto 0);
signal start_d : std_logic;
begin -- behave
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
start_d <= '0';
pass_cnt <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
start_d <= start;
if (start_d = '0' and start = '1') then
pass_cnt <= data;
elsif (pass_cnt != passwd or pass_cnt != (others=> '1')) then
pass_cnt <= pass_cnt + 1;
end if;
end if;
end process;
end behave;