CDC for AXI master and AXI slave

[sun_ray]

My AXI slave is working at 100 MHz. This AXI slave will communicate with AXI masters. Now the AXI masters can
operate at frequencies like 300 MHz, 600 Mhz and 1GHz where the master clock will come from a PLL which is different than the PLL which supplies the slave clock. What are the AXI signals for which CDC can be taken care? What should be used for CDC? It seems double stage synchronizer will not work.

 

[layowblue]

To my understanding, AXI master and slave must work synchronously. I mean, you "might" be able to double/triple sample those hand-shake signals for each channel(addr/data/response), but in your example, the AXI slave will largely impact the efficiency of the whole AXI architecture.
Can you explain the purpose of your current 100MHz AXI slave design?
AMBA AXI Protocol excerpt:

"ACLK Clock source Global clock signal. All signals are sampled on the rising edge of the global clock.
ARESETn Reset source Global reset signal. This signal is active LOW."

 

[ivb1991]

sun_ray, see my reply in other thread: https://www.edaboard.com/threads/312407/#post1338172

 

[sun_ray]

ivb1991 or anybody

That other thread discuss about AXI2AXI bridge and not what was asked in this thread. Can anybody please resolve the issue that is asked in post number 1 of this thread?

Regards

 

[kaiserschmarren87]

Is it possible to use 'AXI Interconnect' in Asynchronous mode ?
According to the Xilinx definition of AXI interconnect, it says:

ACLK Settings — Clock settings of each Master and Slave.

ACLK Asynchronous – Allows you to specify whether the clock for each master/slave is asynchronous or synchronous. This is an optional update parameter. If you provide a selection for one of the masters or slaves, you have to provide a choice for all masters or slaves.
ACLK Ratio — Displays the clock frequency ratio for each Master/Slave.