case statement with repeatation

[sun_ray]

Look at the following case


case (s)

2'b00 y = 1'b1;
2'b00 y = 1'b0;
2'b01 y = 1'b1;
2'b10 y = 1'b0;
2'b11 y = 1'b1;

The case item condition 2'b00 is provided twice.

How will it appear to the simulator and how will it appear to the synthesis tool?

I hear simulator will ignore the second occurence of 2'b00 but synthesis will take care of both the occurence of 2'b00.

 

[rca]

Synthesis tool like Cadence-RC generates an error, not allow.
for Modelsim for example, you could add the parameters "-check_synthesis" during the compilation for simulation which check this king of "error".