[SOLVED] Case statement Verilog

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stark43

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Hello, I see sample codes like this. It got a little weird. Each mipi_clk will have rst_cnt <= 0, but rst_cnt <=1 if the necessary conditions are met. Aren't these processes parallel?

 

Solution
The way that Verilog scheduling works for these non-blocking statements (<=). The RHS of the assignments are computed from top to bottom, and the assignment of these RHS results to the LHS is assigned at the end of the always block.

If a value is updated multiple times the last assignment "wins" and is assigned to the LHS.
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stark43 said:
Hello, I see sample codes like this. It got a little weird. Each mipi_clk will have rst_cnt <= 0, but rst_cnt <=1 if the necessary conditions are met. Aren't these processes parallel?

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The first assignment is default.
The last condition overrides.
 
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Hi,

but in opposite to software code it is not written to "0" and some time later to "1" resulting in a short pulse or glitch.
It is processed at the same time, thus no glitch. Either clean "0" or clean "1" synchronized to posedge of mipi_clk.

Klaus
 
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The way that Verilog scheduling works for these non-blocking statements (<=). The RHS of the assignments are computed from top to bottom, and the assignment of these RHS results to the LHS is assigned at the end of the always block.

If a value is updated multiple times the last assignment "wins" and is assigned to the LHS.
 
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