Cascoded optocoupler feedback for SMPS...optocoupler saturation?

[treez]

In page 9 (bottom right hand side) of the following, it talks about not saturating the optocoupler transistor in the cascaded opto feedback network. Why should it matter if the opto transistor saturates?

https://www.onsemi.com/pub_link/Collateral/AND8273-D.PDF

 

[FvM]

Why should it matter if the opto transistor saturates?

Ruining circuit speed and linearity.

 

[treez]

I didn't think that would apply to an opto-transistor?, I mean the base voltage isn't defined, since the base is not connected, so how can we ever say that the opto-transistor is saturated?

In relation to this....
Regarding Cascoded optocoupler feedback for SMPS's, on page 9, figure 13 of the following document concerning casc0ded optocoupler feedback, which transistor in figure 13 should be prevented from going into saturation?...is it Q1 or the opto-transistor?......the document says its the opto-transistor that should be stopped from saturating, but surely that can't be right?...its surely Q1 which must be prevented from going into saturation?

https://www.onsemi.com/pub_link/Collateral/AND8273-D.PDF

 

[dick_freebird]

You could, I expect, use the optocoupler as an emitter follower
and avoid saturation. Provided that the pin receiving the follower
output is happy with a somewhat reduced output voltage.

If you trigger on the turning-on edge, and your frequency &
min-off-time of the coupler is low enough to let saturation
recovery tun its course, then fine. Triggering on the turnoff
edge is where you'll pick up gross variability.

Best to not let any transistor saturate, because the envelope
of that behavior is usually poorly spec'd and controlled. And
that's before you let the customers at it.

 

[treez]

Thanks , but surely the base voltage of the opto transistor is not defined, and therefore it cannot possibly saturate, since for saturation of the opto transistor , VBE ~ 0.7V and VBC ~ 0.7V, but VB is not defined, so how can VBC and VBE be defined?

 

[mtwieg]

Of course the base potential is defined, it needs to be in order for the band structure of the device to be defined. When Vbc becomes small, then the gain of the transistor will decrease, regardless of whether it's a normal bjt or a phototransistor.

A rough model of a phototransistor has a light-dependent current source from collector to base. That current, along with Vce, will establish a Vbe.

 

[dick_freebird]

Vbe is defined (by photocurrent vs the B-E diode I-V),
it is merely not observable. Vce is directly observable
and you could in under an hour characterize Tr vs
Vce @ Ic, I'm sure. As a rule there is not that much
difference between Vbe and Vbc, 100mV or so, and
you can figure letting Vce get below 200mV is putting
you too close for comfort.

Without base terminal access you have no path to
remove stored charge smartly. That's the real issue.
So don't store any more than you really, really need.

Unfortunately the variability of current transfer coefficient
and degradation over life (let alone any environmental
unpleasantness) tends to make people pack heavy...
too dark is one corner of the box, too slow turning off
is another.

 

[treez]

Figure 1, page 2 of the following shows how an opto is usually hooked up....
https://www.onsemi.com/pub_link/Collateral/NCP1200-D.PDF

...and you can see from this that when the output of the smps goes no-load, then that opto-transistor will definitely saturate....so why do you think figure 1 makes no effort to guard against this saturation of the opto transistor?
I would have thought that the opto-transistor saturation in fig 1 means that the no-load to full-load transient makes the vout plummet to a very low voltage before the opto-transistor gets unsaturated, would you agree?

 

[dick_freebird]

Whether the opto output NPN saturates, depends on what the
chip is doing inside. If (say) there is a hard voltage pinning
circuit (like a cascode emitter, with clamping perhaps) then
the limited collector current (by current transfer ratio and
input current at the LED) could just be "sucked up" and the
device would not saturate. You'd have to inspect waveforms
to see.

Now, the application here is not a switching application at
all, it's a roughly linear voltage feedback of the filtered
output voltage. You would not expect switching behavior
in the opto except under very abnormal conditions, and
with a stable but fast control loop there should not be
enough voltage overshoot to saturate the opto NPN
(the 470 ohm resistor limits the I rise per (V-Vset) to
tolerable degree).