Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

cascode current source Rout logic

Status
Not open for further replies.

yefj

Advanced Member level 4
Joined
Sep 12, 2019
Messages
1,192
Helped
1
Reputation
2
Reaction score
3
Trophy points
38
Activity points
7,199
Hello,i am trying to simulate the lecture circuit shown bellow and i do get the effect shown in the lecture ,i dont understand why saturation point is moving.
we have a bias current so our source point increased.
So i expect the Vgs>Vt threshhold voltage to move also ,because we need to put Vg=Vt+Id*Rs to get the transistor opened .
but as you can see in the simulation bellow it stayed steady.
Why is that?

also why the saturation point is moving mathematickly speaking? and why putting mosfet instead of Rs solves this problem?
Thanks.


1654976020112.png


1654975977791.png
 

So i expect the Vgs>Vt threshhold voltage to move also ,because we need to put Vg=Vt+Id*Rs to get the transistor opened .
but as you can see in the simulation bellow it stayed steady.
Why is that?


Took me a minute to understand his notation (Vd = Va looks like 1/alpha etc...).
When you say bias point, I assume you mean the saturation pt@Vd on the Id vs Vd scale.

for M1, let deltav = Vgs-Vt
= Vg-Vs-Vt
= Vg - RsId -Vt (1)
and Vd = RsId + deltav (2)
subst 1 into 2
Vd = RsId + Vg-RsId -Vt
Vd = Vg - Vt
Notice there is no dependency on RsId here. So that saturation point@Vd is constant regardless of Rs.

However, VGS does move if you keep VG constant as in the notes. And Current slope is getting flatter with higher Rs as expected. However, current is also moving down as Vout/Rout is getting smaller with larger Rout - so it's not necessarily a good current source as each increase of Rs requires a larger Vg to maintain the same current.

A cascoded mosfet device configuration will have a high total fixed output resistance at the drain, corresponding to aspect ratio and gate bias pts. (assuming both devices are properly biased and in saturation). Equivalent to just operating with one Rs = rds value (made larger by gain path) for source device.

* not sure what you are trying to achieve by sweeping Vg in your simulation. You should sweep the Vd and keep Vg fixed.

saturation_sweep.PNG



 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top