Samu
Newbie level 1
Sharing Generics
Hello Ladys and Gents
Is it possible to carry a common generic across multiple components in VHDL?
For example
File A
Entity bla is
generic (size: integer := 16);
Port(a: in std_logic_vector(0 to size-1);
b: in std_logic_vector(0 to size-1)
s: out std_logic_vector(0 to size-1));
end entity bla;
and introduce that generic in file A into this file, File B
Entity blabla is
port(c: in std_logic_vector(0 to size-1); -- I want to implement Generic(Size) from
d: in std_logic_vector(0 to size-1); -- File A
x: out std_logic_vector(0 to size-1));
end entity blabla;
thanks a lot in advance
Samu
Hello Ladys and Gents
Is it possible to carry a common generic across multiple components in VHDL?
For example
File A
Entity bla is
generic (size: integer := 16);
Port(a: in std_logic_vector(0 to size-1);
b: in std_logic_vector(0 to size-1)
s: out std_logic_vector(0 to size-1));
end entity bla;
and introduce that generic in file A into this file, File B
Entity blabla is
port(c: in std_logic_vector(0 to size-1); -- I want to implement Generic(Size) from
d: in std_logic_vector(0 to size-1); -- File A
x: out std_logic_vector(0 to size-1));
end entity blabla;
thanks a lot in advance
Samu