Personally I doubt the parasitics matter to anything with
the possible exception of any dynamic clamps' actuation
time. And that has not to do with parasitics at the pin,
but down the line in the trigger network.
It's a common reaction to try and blame externalities
like models and parasitics, but a little failure analysis
(along with maybe some finer steps in ESD threat
voltage to creep up on the first fail signature, before
catastrophic follow-on events obliterate useful evidence)
would serve you far better than making and chasing
convenient "it's not my design, not my fault" excuses.
If you want to chase CAD related issues I'd start with
the question of whether each pad cell was "blessed" or
"invented", whether every pad-attached device in the
I/O ring has followed ESD design rules, whether current
loops are universally closed at low voltage (ground and
supply domains especially). You might back up and see
whether GGNMOS clamps actually display reasonable
SPICE behaviors and do a full pin-pin nested zap-loop
to show what the weakest pins (i.e. ones that exceed
BVox under threat stimulus) really are, and whether the
loci coincide with the F/A identified fail sites.