Capacitance mismatch: deciding a sandwich or mos cap size

Status
Not open for further replies.
P

patato

Junior Member level 2
Joined
Apr 6, 2006
Messages
22
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,452
capacitance mismatch

I am trying to choose an optimum capacitor value for my pipeline ADC,
and is currently working on capacitance mismatch

how do u guys decide a sandwich or mos cap size to get cap mismatch lower than , say 0.1%?
is there a good way to estimate mismatch by hand-caculation?
 

cap mismatch

I don't think the mos capacitance fit for sample cap. if u use MIM or Poly to poly cap. you can lookup the mismatch form that from foundry.
I think if ur ADC not high speed or high resolution, and you layout better, their ratio can match to 0.1%.
 

    P

    patato

    Points: 2
    Helpful Answer Positive Rating
Re: capacitance mismatch?

jerryzhao said:
I don't think the mos capacitance fit for sample cap. if u use MIM or Poly to poly cap. you can lookup the mismatch form that from foundry.
I think if ur ADC not high speed or high resolution, and you layout better, their ratio can match to 0.1%.
Click to expand...

Thanks Jerry.
Well I did find mismatch form of MIM,but only logic process is available to me..
so i guess i'll have to get along with MOS or sandwich cap(such as M3-M4-M5 or M1-M2-M3).

more question:
1.MOS don't fit sample cap? why?
I've read some paper from Paul.R.Gray's lab, and they said MOS cap has enough linearity for a 10 bit ADC.

2.When it comes to SANDWICH cap, the problem is: no mismatch data for it!
so i am trying to estimate SANDWICH cap' mismatch.
Like this : for a M1-M2 cap , top and bottom plate width=W , length= L
σ of (δW/W)=x
σ of (δL / L)=y

σ of (δC/C) ≈ ( x² + y²)½
is it reasonable?
 

Re: capacitance mismatch?

If you only use the MOScap sample, maybe is enough linearity .but you know the moscap's C_V character, you must contral the gate voltage region. otherwise it voltage character not better.
I think the sandwich cap is better.but it like you say no mismatch data.
I find some company's pipeline ADC datasheet write it use sandwich cap in logic process. I never design the pipeline ADC use sandwich cap in logic process .
So I am sorry, can't help you.
 

capacitance mismatch?

please if u have any papers that useful for using capacitor and its characteristic curves?
please send them to this e-mail
eng_wam2020@yahoo.com
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…