kalbun
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In a 3rd order PLL loop filter, the last capacitor is put in parallel to the VCO input.
But doing so, aren't we modifying the VCO frequency range? Or must this capacitor be taken into account at design stage?
Maybe an RF engineer will consider this as an idiot's question, indeed RF is not my job (nonetheless for various reasons I am in strong need to learn some RF basis 8O)
But doing so, aren't we modifying the VCO frequency range? Or must this capacitor be taken into account at design stage?
Maybe an RF engineer will consider this as an idiot's question, indeed RF is not my job (nonetheless for various reasons I am in strong need to learn some RF basis 8O)