Error: Error: Can't perform simulation of IP file /home/phung/Documents/fpga_overlay/riffa/fpga/altera/de4/DE4Gen2x8If128/ip/PCIeGen2x8If128_core.v because no simulation model files were detected
Error: Error: You did not generate the simulation model files or you generated the IP file using an older version of Intel FPGA IP which is not supported by RTL NativeLink Simulation
Error: Error: Regenerate the IP and simulation model files using the latest version of Intel FPGA IP for RTL NativeLink Simulation flow to function correctly
Error: Error: NativeLink simulation flow was NOT successful