preethi19
Full Member level 5
Cant fit design in device - error re pins
Hi i am learning about working with FPGA's and i am trying a simple or gate logic. Following is the code
I somehow managed to assign the pins to the inputs and output of the or gate. After assigning the pin location when i run "start I/O assignment analysis", i am getting an error saying "can't fit design in device". I read the cause of this problem and it was posted that there might be error in source code. But after writing the VHDL code when i run compilation i dont get any errors and it is successful. But after assigning pins when i do that it is failing. I assigned the pins according to the kits manual for the FPGA pins. Can anyone please help me out with this problem. Thank you!!!
Hi i am learning about working with FPGA's and i am trying a simple or gate logic. Following is the code
Code:
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: name, inputs, outputs
entity orGate is
port( A, B : in std_logic;
F : out std_logic);
end orGate;
--FUNCTIONAL DESCRIPTION: how the OR Gate works
architecture func of orGate is
begin
F <= A or B;
end func;
I somehow managed to assign the pins to the inputs and output of the or gate. After assigning the pin location when i run "start I/O assignment analysis", i am getting an error saying "can't fit design in device". I read the cause of this problem and it was posted that there might be error in source code. But after writing the VHDL code when i run compilation i dont get any errors and it is successful. But after assigning pins when i do that it is failing. I assigned the pins according to the kits manual for the FPGA pins. Can anyone please help me out with this problem. Thank you!!!
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