no i have not simulated. but i get this ports in my top hdl properly. it shows all ports in my instance (.vho) file.
problem is arises only when i making any of MB port as external. my code is synthesizes, also then generates bit stream file. after that i am transferring in SDK with bit stream file then it get programmed but there is no output from kit. also it does not give any error. if taking into debugging mode it stays in continues running mode.
thanks