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can't able use external ports, seems error in kintex 7.

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shashirai_xilinx

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Hi
I am working with the kintex-7 mini module plus kit and using ISE 14.1.

I have used a MB core within the ISE project. I am trying to use a extra BRAM and BRAM controller IP cores (apart from default BRAM) of micro-blaze processor. I have connected one port of BRAM to the MB processor through BRAM controller and another port of BRAM are made external to access form HDL module. The design is not working.

The problem comes as soon as I make any port of IPs as external. The existing program running earlier (tested simple LED program) stops working when I add extra BRAM and BRAM controller IP cores and make BRAM ports external. If I leave these ports unconnected, program again starts working.

Not only the BRAM port, any other pins of MB processor causes same problem if assigned as external port. Why it is behaving like this? Is there any issue in using ports as external? Is there any setting for making the ports as external?

Please resolve the issue as soon as possible.
also attach solution in screen shot

thanks
 

barry

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Have you simulated this? Any errors when you compile it?
 

shashirai_xilinx

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no i have not simulated. but i get this ports in my top hdl properly. it shows all ports in my instance (.vho) file.

problem is arises only when i making any of MB port as external. my code is synthesizes, also then generates bit stream file. after that i am transferring in SDK with bit stream file then it get programmed but there is no output from kit. also it does not give any error. if taking into debugging mode it stays in continues running mode.

thanks
 

dpaul

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no i have not simulated. but i get this ports in my top hdl properly. it shows all ports in my instance (.vho) file.

Please do the simulation first. There is no point in doing synth and then PaR if the simulation model doesn't work. This is the philosophy of hardware design, you cannot assume things and one needs to take baby-steps for the entire development process.
 

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no i have not simulated. but i get this ports in my top hdl properly. it shows all ports in my instance (.vho) file.

problem is arises only when i making any of MB port as external. my code is synthesizes, also then generates bit stream file. after that i am transferring in SDK with bit stream file then it get programmed but there is no output from kit. also it does not give any error. if taking into debugging mode it stays in continues running mode.

thanks

Too many newbies focus on ERRORs, WARNINGS are usually even more important to look at! Those warnings like removing yadayada because it's not driven means half your design just went bye bye.
 

shashirai_xilinx

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sir, i did not get your point of simulation.
please i tell me how can i simulate this port ?
and which tool i have to use for the simulation ?
 

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sir, i did not get your point of simulation.
please i tell me how can i simulate this port ?
and which tool i have to use for the simulation ?
In ISE it's called ISIM. Or you could use something like Modelsim if you have it available.

I hope you aren't expecting a step by step tutorial on running an ISIM simulation...Xilinx already provides such documementation.
 

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