Hi all.
I am using a 1-port RAM created using Altera Quarus 16 Lite(IP Catalog). It has width of 16 bits and depth of 64 words. I store in data from a computing register in it and want to read it after some time as I will use this data as input for another module. The data transmission is fine but as I make write_enable '0' and read_enable '1', I receive only first and last data bytes(and middle 1-62 data is lost). But If I make write_enable '1' and read_enable '1' its working fine with a delay of 1 cycle. I do not understand if I am really saving data in RAM or not. Here is behavioral code.Here is the link **broken link removed** to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.
Thanks in advance.
You use en as both a write enable and as a clock enable. Using rst1 as a control signal to reset the address is a poor design choice.
Next time post the code on edaboard. Use code or syntax (preferred) tags. They are applied by placing the following tags around your code. Note remove all spaces (spaces added to keep the tags from taking effect).