Cannot open include file "timescale.v, i2c_master_defin

[nareshgtr]

Dear All.
When I am simulating the Verilog project (with "include files" in the project) in Questasim simulator, I am getting the following Error
Error: E:/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v(138): Cannot open `include file "timescale.v".
** Error: E:/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v(141): Cannot open `include file "i2c_master_defines.v"
Please some one explain why I am getting this error.
Regards
V. Naresh Kumar

 

[prashanthv]

Re: Questasim simulator - error explain needed

Hi Naresh,

Were you successful in addressing the above error? coz am getting the same error too though the file referred to is very much there.

.../code/proto_drv.sv(3): Cannot open `include file "proto_pkt.sv".

as a work around i tried putting all classes into packages and importing relevant packages in the code file where i use that class and it works. But thats not the solution.

Not sure whats wrong. Could certainly use some help here.

Thx,
Prashanth

 

[prashanthv]

Re: Questasim simulator - error explain needed

Ok got it. Use the absolute path within double quotes.

eg: `include "c:\\project\\sv\\code\\proto_pkt.sv"

Please note the "\\" (double backslash) one of it used as an escape character in the regular absolute path.

A reference to this has been made in the LRM in section "25.3 ‘include"

Hope this helps.

Thx,
Prashanth

 

[nareshgtr]

Re: Questasim simulator - error explain needed

Thanks prashanth.
Regards
V. Naresh Kumar