UFSTY
Newbie
Hello I am new using VHDL, and when i was trying to simulate it in ModelSim, but then a fatal error occur.
It didnt give me error when compile.
Here is what it says:
--------------------------------
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/Usuario/Desktop/Modelsim/examples/trabajo/dec3_8_modelo.vhd 36 Process line__22
#
--------------------------------------
And here is my code:
I don´t know where my error is, or what i did wrong. I was trying to do a decoder 3:8.
Thanks if you read and help. ^^
It didnt give me error when compile.
Here is what it says:
--------------------------------
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/Usuario/Desktop/Modelsim/examples/trabajo/dec3_8_modelo.vhd 36 Process line__22
#
--------------------------------------
And here is my code:
Code:
---------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
--Entidad--
entity dec3_8 is
GENERIC (retardo:TIME:= 0 ns);
port (
--Entradas--
E:in std_logic;
C:in std_logic_vector(2 downto 0);
--Salidas--
S: out std_logic_vector(7 downto 0) );
end dec3_8;
--Arquitectura--
architecture dec3_8_arq of dec3_8 is
--Declarativa: ---
begin
process(E,C)
begin
if (E = '1') then
S <= "11111111";
else
case C is
when "000" => S <= "01111111";
when "001" => S <= "10111111";
when "010" => S <= "11011111";
when "011" => S <= "11101111";
when "100" => S <= "11110111";
when "101" => S <= "11111011";
when "110" => S <= "11111101";
when "111"=> S <= "11111110";
when others => S <= "0000";
end case;
end if;
end process;
end dec3_8_arq;
----------------------------------------------------I don´t know where my error is, or what i did wrong. I was trying to do a decoder 3:8.
Thanks if you read and help. ^^
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