Can we use the sine wave generated by IP cores for PWM generation in Verilog?

[keerthna]

I want to use PWM using sine triangle generation. If I generate sine waves using Ip cores can that sine wave be instantiated in another module which generates the triangle waves? I mean without writing a test bench can we connect these signals in Verilog?

 

[sharath666]

Please make yourself more clear.

 

[keerthna]

I have one verilog module which generates the sine wave using the ip cores from xilinx. I now create another verilog module which generates a triangle wave and uses the sine wave generated previously for the pwm generation. Is this possible without creating a test bench? Also can the modulation index of the sine wave be changed on the fly using ipcores?

 

[sharath666]

I suppose you can. I don't know what your concept of testbench is. Testbench is kind of a wrapper around the RTL DUT. It is basically used for testing the DUT. The tasks it usually does are provide the clock,reset to the DUT, initialize the DUT, provide the triggers to the DUT and sample the outputs.
I don't know how is a testbench related to your question.
If the modulation index is register programmable, it should be possible to change it on the fly.

 

[keerthna]

I MEANT THAT THE TEST BENCH CAN ONLY BE SIMULATED. HOW CAN I SYNTHESIZE IT? i mean i want to synthesize the code using spartan6 fpga. so if i write a test bench, how can i synthesize?

 

[sharath666]

Oh. Looks a like a follow up question to something you asked days back. So this was ur question !!
Synthesize it just as you are synthesizing your rtl. The top file here will be your testbench file.