# Can we make this huge verilog code(32 bit multiplier) into small one?

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#### rokyslash

##### Newbie level 1
I am a beginner when it comes to verilog and i have found this 32 bit multiplier code(using CSLA logic:it seems, thats what a friend of mine said). Is there a way to reduce the code: i mean by using for loops or any other method. I am doing this for my academic project and i need some expert help if there is a way i can reduce this.

P.S I am new to such forums and stuff, so please forgive me if i am posting things in a wrong way or anything.

Here is the code attached and it has simple AND gate,half and full adder modules in this.

#### Attachments

• multiplier.txt
52.2 KB · Views: 10

#### vGoodtimes

##### Advanced Member level 4
For FPGAs, you can (and likely should) use "*" with the appropriate types. This is because there are multiply units already in the FPGA. These multiply units have dedicated logic and routing. As a result, it will be hard to make a better multiplier out of normal LUTs and normal routing resources.

##### Super Moderator
Staff member
As vGootimes said the FPGA equivalent to the huge, un-maintainable mess of structural Verilog, would be this:

Code Verilog - [expand]1
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module multiplier (
input  [31:0] a,
input  [31:0] b,
output [63:0] p
);

assign p = a * b;

endmodule

But if you want high performance you'll probably want to add a clock and include some pipeline registers.

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