Initializing implies constant expressions, not input signals. If the inputs are connected to a constant in your design hierarchy, it may possibly work.
Thanks for the answer...But how can we use arrays in the design.......if i want to delcare an array as an output how can i declare that..
example: output [15:0]w1 [1:0];
wire w1[1:0];
is this a valid syntax.
Standard Verilog doesn't allow structurized signals, e.g. arrays or records, for interfaces. You have to convert them to one dimensional bit vectors for in-and output.