Feb 7, 2013 #1 M mail4idle2 Full Member level 4 Joined Oct 20, 2012 Messages 200 Helped 20 Reputation 40 Reaction score 19 Trophy points 1,298 Activity points 2,173 Can we Force Integer in Verilog simulation from Verilog Testbench
Feb 7, 2013 #2 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 841 Helped 366 Reputation 736 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,390 Yes. Next question.