A lateral BJT with base width under a micron, is probably
only going to be geometry-repeatable when drawn as a
self-aligned structure. That means a MOS gate over the
base region, a lightly doped (rather than mid-doped)
base and a high pinched base resistance. Possibly suitable
for a very low bandgap current, but with the gate over
base it will probably not be very well fitted by plain BJT
models, and have poor high frequency response. The
beta will track "channel length" (base width) and the useful
"emitter area" is going to swing with emitter current with
debiasing; very low currents, it will be the emitter (source)
sidewall plus some portion of the bottom plate, but at
higher the debiasing will "kill" all but the sidewall. So your
knee current will be low.
Verticals are better but you would need a process with
nested wells to get three free terminals. The "freebie"
subPNP is the usual option because it's there. But you
have only the two E, B terminals free and the collector
pinned to Vsub. And foundries generally have tried to kill
the beta in parasitic vertical devices as much as they
can, for latchup suppression. And it's not generally a good
idea to be injecting current to the substrate. If you are
using subPNPs some stiff guardringing is a good idea.
You can also make bandgaps with plain diodes. Their
linearity is probably a lot poorer, at least it has been in my
experience with using gated diodes. A vertical P+/Nwell
diode with a good N+ guardring at PSub potential, and a
P+ guardring outside, might be a reasonable bandgap
reference element that you can find examples for model
tweaking, for. You have to make up the gain in a CMOS
op amp and not count on any from the element itself.
I have gotten semi-decent LBJT-as-diode results from
body-tabbed NMOS run in reverse, but the style is probably
not allowed in any deeper submicron technology (I broke
the rules in my fab). The intradevice beta can be high
even at 1um, it's the huge base resistance that kills the
-evident- beta before it ever really gets up on peak. If you
can interdigitate N+ and P+ slugs in the source, legally,
and tie the gate to source as well, then you have a transdiode
that will probably give you enhanced log-linearity (a must
when operating at highly different current densities as a
bandgap wants). Not usable as a gain transistor, but using
the gain as an improver for other qualities.