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Can we create an npn BJT in the layout instead of using one?

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Aug 21, 2009
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Hi , I didn't know how to write it properly in the title. I have a problem. The BJTs I use, have very very small beta (think about 1) which destroys my results. I want to use them in a bandgap reference. So when I connect in parallel 8 BJTs nothing happens in the bandgap core. I use the cadence tool.

I want to know if there is a possibility to create npn or pnp transistors by myself, without using the technology's models so as to get a good beta. I know it is difficult, I just want some info. I've heard I can not create pnp. I think I can just make npn, with the use of epitaxial layer and a deep n well..something like that. This is not clear to my mind, can somebody help? where can I get some more info?

Re: Can we create an npn BJT in the layout instead of using

I don't think that you can duplicate the silkscreening methods that are done on a microscopic level when manufacturing semiconductors. Transistors (npn, pnp, bjt, MOSFETs ect) like other semiconductors (Microcontrollers, op amps ect) are all manufactured using very stringent techniques using multimillion dollar equipment including clean rooms and such. The actual circuits which National semiconductor, or Intel, or say Texas Instruments use in their products are so tiny that they are microscopic (including npn, pnp, bjt, MOSFETS transistors). It would be humanly impossible to get the positive semiconductive material close enough to the negative semiconductive material to actual make a diode or part of a transistor. It would be neat to be able to build your own but I really don't think that's possible.

In general each CMOS technology incorporate a number of devices, usually defined as parasitics,- it could be bipolar pnp and npn, vertical or lateral. For example, each PMOS reperesents also lateral pnp with beta >> 1. Typically vertical pnp only is included in fab model's file, and it have beta ~ 1.
All other structures could be characterized and models could be built by you themself of course. But it will require a lot of efforts: test chip with appropriate set of structures, measurement equipment, software and skilled specialists to build own models,... It is expensive and time consuming.
From other side without correct models it is very risky to use such devices in design. So most designers have very limited freedom in using devices, which aren't described in fab's model file.
You can try to request fab's support for structures, which you would like to use. Sometimes an auxiliary not official information can be evailable.

A lateral BJT with base width under a micron, is probably
only going to be geometry-repeatable when drawn as a
self-aligned structure. That means a MOS gate over the
base region, a lightly doped (rather than mid-doped)
base and a high pinched base resistance. Possibly suitable
for a very low bandgap current, but with the gate over
base it will probably not be very well fitted by plain BJT
models, and have poor high frequency response. The
beta will track "channel length" (base width) and the useful
"emitter area" is going to swing with emitter current with
debiasing; very low currents, it will be the emitter (source)
sidewall plus some portion of the bottom plate, but at
higher the debiasing will "kill" all but the sidewall. So your
knee current will be low.

Verticals are better but you would need a process with
nested wells to get three free terminals. The "freebie"
subPNP is the usual option because it's there. But you
have only the two E, B terminals free and the collector
pinned to Vsub. And foundries generally have tried to kill
the beta in parasitic vertical devices as much as they
can, for latchup suppression. And it's not generally a good
idea to be injecting current to the substrate. If you are
using subPNPs some stiff guardringing is a good idea.

You can also make bandgaps with plain diodes. Their
linearity is probably a lot poorer, at least it has been in my
experience with using gated diodes. A vertical P+/Nwell
diode with a good N+ guardring at PSub potential, and a
P+ guardring outside, might be a reasonable bandgap
reference element that you can find examples for model
tweaking, for. You have to make up the gain in a CMOS
op amp and not count on any from the element itself.

I have gotten semi-decent LBJT-as-diode results from
body-tabbed NMOS run in reverse, but the style is probably
not allowed in any deeper submicron technology (I broke
the rules in my fab). The intradevice beta can be high
even at 1um, it's the huge base resistance that kills the
-evident- beta before it ever really gets up on peak. If you
can interdigitate N+ and P+ slugs in the source, legally,
and tie the gate to source as well, then you have a transdiode
that will probably give you enhanced log-linearity (a must
when operating at highly different current densities as a
bandgap wants). Not usable as a gain transistor, but using
the gain as an improver for other qualities.
Re: Can we create an npn BJT in the layout instead of using

Thank you for the answers. Of course it costs, and I wouldn't fabricate it, I just wanted to know how this can be done by the cadence tool. Freebird you're always so analytical, thanx!

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