You use a "virtual" clock to define a clock driving an input to your module. If that clock is different from the source clock inside your module, then timing analysis will automatically take that into account.
Now the "virtual" clock may be different due to phase offsets, or it may be different in frequency, or some combination of both.
Well defined just means that you have some constraints on the phase relationship. Like from a PLL databook. Or if you know that the clock tree of the source module, you can usually compute min/max clock insertion delay.
Terry